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Posts Tagged ‘Accellera’

Portable Stimulus

Thursday, March 23rd, 2017

Gabe Moretti, Senior Editor

Portable Stimulus (PS) is not a new sex toy, and is not an Executable Specification either.  So what is it?  It is a method, or rather it will be once the work is finished to define inputs independently from the verification tool used.

As the complexity of a system increases, the cost of its functional verification increases at a more rapid pace.   Verification engineers must consider not only wanted scenarios but also erroneous one.  Increased complexity increases the number of unwanted scenarios.  To perform all the required tests, engineers use different tools, including logic simulation, accelerators and emulators, and FPGA prototyping tools as well.  To transport a test from one tool to another is a very time consuming job, which is also prone to errors.  The reason is simple.  Not only each different class of tools uses different syntax, in some cases it also uses different semantics.

The Accellera System Initiative, known commonly as simply Accellera is working on a solution.  It formed a Working Group to develop a way to define tests in a way that is independent of the tool used to perform the verification.  The group, made up of engineers and not of markting professionals, chose as its name what they are supposed to deliver, a Portable Stimulus since the verification tests are made up of stimuli to the device under test (DUT) and the stimuli will be portable among verification tools.

Adnan Hamid, CEO of Breker, gave me a demo at DVCon US this year.  Their product is trying to solve the same problem, but the standard being developed will only be similar, that is based on the same concept.  Both will be a descriptive language, Breker based on SystemC and PS based on SystemVerilog, but the approach the same.  The verification team develops a directed network where each node represents a test.  The Accellera work must, of course, be vendor independent, so their work is more complex.  The figure below may give you an idea of the complexity.

Once the working group is finished, and they expect to be finished no later than the end of 2017, each EDA vendor could then develop a generator that will translate the test described in PS language into the appropriate string of commands and stimuli required to actually perform the test with the tool in question.

The approach, of course, is such that the product of the Accellera work can then be easily submitted to the IEEE for standardization, since it will obey the IEEE requirements for standardization.

My question is: What about Formal Verification?  I believe that it would be possible to derive assertions from the PS language.  If this can be done it would be a wonderful result for the industry.  An IP vendor, for example, will then be able to provide only one definition of the test used to verify the IP, and the customer will be able to readily use it no matter which tool is appropriate at the time of acceptance and integration of the IP.

DVCon Is a Must Attend Conference for Verification and Design Engineers

Monday, February 13th, 2017

Gabe Moretti, Senior Editor

Dennis Brophy, Chair of this year’s DVCon said that “The 2017 Design and Verification Conference and Exhibition U.S. The conference will offer attendees a comprehensive selection of 39 papers, 9 tutorials, 19 posters, 2 panels, a special session on Functional Verification Industry Trends, and a keynote address by Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group at Cadence.”

DVCon is   sponsored by Accellera Systems Initiative, DVCon U.S. will be held February 27-March 2, 2017 at the DoubleTree Hotel in San Jose, California.

DVCon was initially sponsored by VHDL International and Open Verilog International; but its growth really started after the two organizations merged  to form Accelera which was renames Accellera Systems Initiative during its merger with Open SystemC Initiative.  It seems that every EDA organization now-a-days needs the word “systems” in its name.  As they are afraid to be seen to be of lesser importance without making very sure that everyone knows they are aware of the exitance of systems.

DVCon is now a truly international conference holding events not only in the US but also in Europe, India and, for the first time this year, in China.

The aim of Accellera is to build and serve a community of professionals who focus on development and verification of hardware systems, with the awareness that software role in system design is growing rapidly.  Dennis Brophy observed that “Coming together as a community is fostered by the DVCon Expo. The bigger and better exposition will run from Monday evening to Wednesday evening. See the program for specific opening and closing times. The Expo is a great place to catch up with commercial vendors and learn the latest in product developments. It is also great to connect with colleagues and exchange and share information and ideas. Join us for the DVCon U.S. 2017 “Booth Crawl” where after visiting select exhibitors you will be automatically entered for a lucky draw.”

Although the titles of the papers presented in the technical conference focus on EDA technologies, the impact of the papers deal with application areas diverse from automotive to communications, from the use of MEMS and FPGA in system design, from could computing to rf.

“DVCon has long been the technical and social highlight of the year for design and verification engineers,” stated Tom Fitzpatrick, DVCon U.S. 2017 Technical Program Chair.  “Through the hard work of a large team of dedicated reviewers, we have chosen the best of over one hundred submitted abstracts from deeply knowledgeable colleagues within the industry to help attendees learn how to improve their verification efforts. We also have two days of extended tutorials where attendees can get an in-depth look at the cutting edge of verification, not to mention the Exhibit Floor where over 30 companies will be demonstrating their latest tools and technologies.  In between, there are plenty of opportunities to network, relax and take advantage of a fun and welcoming atmosphere where attendees can reconnect with old friends and former colleagues or make new friends and contacts. The value of DVCon goes well beyond the wealth of information found in the Proceedings. Being there makes all the difference.”

Dennis Brophy added that on Monday February 27th there will be a presentation covering the Portable Stimulus work being done under Accellera sponsorship.  The working group has made significant progress toward defining what it is and how it works.  The goal is to have the Board of Accellera to authorize a ballot to make the result an industry standard and to further take it to the IEEE to complete the standardization owkr.

As has happened last year the exhibit space was quickly filled by vendor who understood the advantage of talking with technologists who specialize in verification and design of complex systems.

Devgan’s keynote, “Tomorrow’s Verification Today” will review the latest trends which are redefining verification from IP to System-level with an increasingly application-specific set of demands for hardware and software development. Over the past decade, verification complexity and demands on engineering teams have continued to raise rapidly. However, the supporting automation tools and flows have been only improving incrementally, resulting in a verification gap. It is time to redefine how verification should be approached to accelerate innovation in the next decade.  In his presentation, Dr. Devgan will review the latest trends which are redefining verification from IP to System-level, with an increasingly application-specific set of demands changing the landscape for hardware and software development. The keynote will be delivered on Tuesday, February 28

On the same day from 1:30-2:30pm in the Oak/Fir Ballroom the conference will offer a special session with Harry Foster, Chief Scientist for Mentor Graphics’ Design Verification Technology Division.  Foster has been asked to present “Trends in Functional Verification: A 2016 Industry Study” based on the Wilson Research Group’s 2016 study. The findings from the 2016 study provide invaluable insight into the state of today’s electronics industry. It will be held on Tuesday, February 28 from 10:30-11:00am in the Fir Ballroom.

Two full days of in-depth tutorials: Accellera Day with three tutorials on Monday and sponsored tutorials on Thursday.  There are also many technical papers and posters and two intriguing panels.

There will be plenty of networking opportunities, especially during the exhibition.  There will be a booth crawl on Monday, February 27 from 5:00-7:00pm and receptions both Tuesday and Wednesday in the exhibit hall.  Exhibits will be open Tuesday from 5:00-7:00pm and Wednesday and Thursday from 2:30-6:00p

The awards for Best Paper and Best Poster will be presented at the beginning of the reception on Wednesday.  For the complete DVCon U.S. 2017 schedule, including a list of sessions, tutorials, sponsored luncheons and events, visit www.dvcon.org.

Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License

Monday, August 15th, 2016

Gabe Moretti, Senior Editor

SystemC is a subset of the C language.  The C language is widely used by software developers.  The SysremC subset contains the features of C that are synthesizable, that is, they are useful to describe hardware components and designs.  SystemC is used mainly by designers working at the system level, especially when it is necessary to simulate both hardware and software concurrently.  An algorithmic description in SystemC of a hardware block generally simulates faster than the same description implemented in a traditional hardware description language.

Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, just announced that all SystemC supplemental material, including material contributed under the SystemC Open Source License Agreement prior to the merger of the Open SystemC Initiative (OSCI) and Accellera in 2011, has now been re-licensed under the Apache License, version 2.0.

The SystemC Open Source License used for the supplemental material required a lengthier contribution process that will no longer be necessary under Apache 2.0. Other Accellera supplemental material already available under Apache 2.0 includes the Universal Verification Methodology (UVM) base class library.

“This is a significant milestone for Accellera and the SystemC community,” stated Shishpal Rawat, Accellera Systems Initiative chair. “Having all SystemC supplemental material, such as proof-of-concept and reference implementations, user guides and examples, under the widely used and industry-preferred Apache 2.0 license will make it easier for companies to more readily contribute further improvements to the supplemental material.  We have been working with all of the contributing companies over the past 18 months to ensure that we could offer SystemC users a clear path to use and improve the SystemC supplemental material, and we are very proud of the efforts of our team to make this happen.”

The supplemental material forms the basis for possible future revisions of the standard as new methods and possible extensions to the language are adopted by a significant majority of users.  It is important to keep in mind that a modeling language is a “living” language, which means that it is subject to periodic changes.  For example, the IEEE specifies that an EDA modeling language standard be reaffirmed every five years.  This institutionalizes the possibility of a new version of the standard at regular intervals.

ESDA to Host System Scaling Forum

Wednesday, May 4th, 2016

Gabe Moretti

Not too long ago EDAC was a quite consortium that only bothered analysts and journalists by issuing EDA market reports.  Since Bob Smith became its executive director it seems that not one week passes without another press release reaches my inbox.  First there was the name change, from EDAC to ESDA, just a little further down the alphabet.  Then there was a marketing agreement with SEMICO and the appointment of Lucio Lanza to the ESDA board.  Both with the aim to convince IP companies to join ESDA.  The easoning went something like this: ”We serve the same market, so why not collaborate?”

The latest move is to organize a working group on System Scaling.  No one knows what the working group mission is, but why not try something as long as it generates news.  So now ESDA seems to want to compete with Accellera, probably a very bad idea given the overlap of membership between the two organization at the board of directors level.  As usual ESDA did not ask for my advice.  Had they done so I would have told them to explore a working relationship with Accellera.  They have more experience in running successful working groups than most other organizations and ESDA might even gather a few suggestions on how to improve DAC, seen the results DVCon is producing worldwide.

The meeting is scheduled for May 17, from 6 to 8 PM at the impressive sounding ESDA Global Headquarters, 3081 Zanker Road in San Jose.  The evening is free of charge and open to members of the design and manufacturing community interested in system scaling.  Herb Reiter of EDA2ASIC Consulting will conduct the Forum that has been titled “More than Moore –– Enabling the Power of System Scaling”.  I called Herb to find out what “system scaling” is all about.  He told me that 3D and 2.5D Packaging is what he means when he talks about system scaling.  The idea is to package systems in a smaller volume.  The system is scaled to smaller dimensions thus the name.  He has authored a Multi-die IC design Guide of over 300 pages on the subject.  The volume can be downloaded from the eda2asic.com site free of charge.  The scope of the forum is to seek community input on direction and priorities for the System Scaling Working Group.

To be sure 3D and 2.5D packaging present a number of challenges to designers and verification engineers.  Place and route, power distribution, signal integrity are all issues found not only with traditional dies, but also on printed circuit boards (PCB).  Are the tools used today to analyze and solve these types of issues sufficient?  Is there human interface adequate?  How can the total system into which these packages are integrated be simulated while still maintaining the identity of each individual die?  I am sure there are more issues than just these, but the issue remains how an organization that has never run a technical working group can be efficient and effective from the start.

Lucio Lanza Joins ESDA Board

Friday, April 22nd, 2016

Gabe Moretti, Senior Editor

In a major change of the board structure, the Electronic System Design Association (ESDA) has elected Dr. Lucio Lanza to its Board of Directors.  Previously the Board members were only officers, and in most cases CEOs of member companies, but in an effort to broaden the outlook of the board to encompass ESDA’s new mission a new prospective on the electronic industry is required.

Dr. Lanza, the 2014 Phil Kaufman award winner, has spent all of his professional career in the electronic industry and is now a leading Silicon Valley venture capitalist and industry observer.  I asked Lucio the reason for his decision to join the ESDA board.  “It is a very important time for the next generation of electronic products. In the next few years we are going to have more products created than in the history of mankind.  The responsibility of organizations like ESDA to help people create those products is pretty significant.  So we need to make sure that we get well organized and we all cooperate.”

As it is typical of Lucio, he looks at the entire scope of the problem and defines organizations like ESDA as principal facilitator of the upcoming major change in the industry.  When Lucio looks at the purpose of what was EDAC he points out that the EDA industry had traditionally concentrated in enabling the electronic industry to step from one process node to the next while maintaining development costs practically flat.   This has been the EDA’s Moore’s Law.  It has been a success, but the challenges are different now, at least for the vast majority of companies and ventures that are looking at developing IoT products.  And one of the signals that the EDA industry has recognized this fact is the change of the EDAC name to ESDA.

Much has already been written about the new name: ESDA, and how there might have been better choices.  Personally I am glad that at the time we did not name Accellera as the Electronic Standards Development Association, or EDAC would really have had a much harder task renaming itself.  But the aim was to make a statement that electronic products are now much more than an orderly collection of silicon transistors, and that engineers require more than traditional EDA tools to efficiently develop them.  So the word “system” provides the best description of the problem to be solved.  The method to develop hardware has changed with the use of IP blocks, and the use of software has increased significantly.  The way Lucio explains it, makes it so clear that now I appreciate what motivated the name change.

Lucio points out that: “The traditional EDA tools are no longer sufficient to fulfill its own Moore’s Law.  In the last few years what engineers needed to design SoCs was availability of IP.  The issue became “Is there the right IP?”  Because up to 80% of the chip is not new development but new or modified IP.  Somehow we ended up designing new chips by assembling IP and designing only a minor portion from scratch.”

In looking at the state of development today Lucio found that many developers are spending ten times more in software than they are in hardware development and debug. He continued by pointing out that this is the problem to be addressed.  His message is that EDA intended as the provider of all development tools and methods, must find a way to bring the IP vendors and the software modules and tools providers to realize that everyone will benefit from a well-planned coordination on the supply side of the equation.

My next question dealt with how could ESDA contact a software tool company and convince it that it is in the common interest to “design together”.  “There are two steps here” said Lucio “the first step, which I cannot say I am an expert in, so I am very very humble, is to find out what is the environment today.  Are there companies that are already trying to do that?  If so, is there something we can do to help these people to acquire visibility?”  The second question is “Is there a way that potential users can encourage these companies and others to strengthen and expand such approach is the follow on question.  Organizations like ESDA must become the leaders in organizing and supporting this work.”

The just announced agreement between ESDA and Semico says Lucio is a way to understand that we are all after the same goals.   “if we cooperate the efficiency of the industry will increase and we all will benefit, not just benefit as businesses, but benefit as society.”

Register Automation: A visit with Semifore

Tuesday, March 29th, 2016

Gabe Moretti, Senior Editor

During the just passed DVCon U.S. I met with Richard Weber, CEO of Semifore (www.semifore.com).  When I was asked to meet with him by Jill Jacobs I thought she was introducing a new company.  I was wrong! Semifore was founded in 2006 and is an on-going healthy company that has now decided to be more open to the press.

Semifore is a small company, only seven full time employees, with the mission to develop technology that significantly reduces cost to develop and verify complete control register automation of complex ASIC, SoC, and FPGA-based design.  The company offers an advanced compiler for specification, verification, documentation, and implementation of configuration, status registers and address maps for complex designs.

Semifore is self-funded, profitable, and with a healthy list of customers that include a significant number of tier 1 companies.  It is not presently seeking third party funding, although I have pointed out that further significant expansion of the business will require a significant investment.  I put the company in the “life-style” bucket, a good group whose recent principal alumnus is Denali.

When Richard told me that Semifore had developed its own language, CSRSpec, all sorts of warning bells went off in my head.  Not another language! I was thinking.  What amount of work would be necessary to get it accepted?  It turned out that my fears were unfounded.  The language not only interfaces with industry standard busses, but also reads and writes SystemRDL, IP-XACT, and spreadsheets.  It produces RTL, firmware header files, verification data, and documentation in HTML, Word, FrameMaker, and others.  In other words, it fits seamlessly into a design flow with third party tools.

Figure 1 How CSRCompiler fits in the design flow

The limitations of IP_XACT are main reason for the new language.  Richard described it as “kicking IP_XACT up a notch (or 10)”.  Actually the description is not quite fair since IP_XACT, and IEEE 1685 its natural derivative, is a “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” does not directly address total register automation.  It is more accurate to say that CSRSpec implements functions as a supplement of the capabilities of IP_XACT.  For sure CSRSpec does a much better job than SystemRDL, a de-facto standard developed by the SPIRIT consortium, whose further development has been ignored by the EDA community.  It is true that within the Accellera System Initiative, a SystemRDL Working Group was formed in 2012, but the group is still seeking members and, to my knowledge, has done no development work so far.

It is clear that niche companies can still find a way to contribute to EDA and in the process generate a respectable revenue stream.  But it takes both ingenuity and dedication.  Before founding Semifore Richard Weber and Jamsheed Agahi worked at Cisco and each have more than twenty years of design and verification experience.  Herb Winsted, VP of business development and Customer Care was a mask designer at AMD and then provided sales support at Cadence, Silicon Valley Research, and Silvar-Lisco.  Rob Callaghan, COO has more than 25 years of experience in the electronic industry, including a stint at Cadence.

DVCon U.S. 2016 Is Around the Corner

Thursday, February 18th, 2016

Gabe Moretti, Senior Editor

Within the EDA industry, the Design & Verification Conference and Exhibition (DVCon) has created one of the most successful communities of the 21st century.  Started as a conference dealing with two design languages, Verilog and VHDL, DVCon has grown to cover all aspects of design and verification.  Beginning as a conference based in Silicon Valley, the conference is now held on three continents: America, Asia and Europe.  Both DVCon Europe and DVCon India have shown significant growth, and plans are well on their way to offer a DVCon in China as well.  As Yatin Trivedi, General Chair of this year’s DVCon U.S., says, “DVCon continues to be the premier conference for design and verification engineers of all experience levels. Compared to larger and more general conferences, DVCon affords attendees a concentrated menu of technical sessions – tutorials, papers, poster sessions and panels – focused on design and verification hot topics. In addition to participation in high quality technical sessions, DVCon attendees have the opportunity to take part in the many informal, but often intense, technical discussions that pop up around the conference venue among more than 800 design and verification engineers and engineering managers. This networking opportunity among peers is possibly the greatest benefit to DVCon attendees.”

Professionals attend DVCon to learn and to share, not just to show off their research achievements as a community.  The conference is focused on providing its attendees with the opportunity to learn by offering two days of tutorials as well as frequent networking opportunities.  The technical program offers engineers examples of how today’s problems have been solved under demanding development schedules and budgets.  Ambar Sarkar, Program Chair, offers this advice on the DVCon U.S. 2016 web site: “Find what your peers are working on and interact with the thought leaders in our industry. Learn where the trends are and become a thought leader yourself.”

Grown from the need to verify digital designs, verification technology now faces the need to verify heterogeneous systems that include analog, software, MEMS, and communication hardware and protocols.  Adapting to these new requirements is a task that the industry has not yet solved.

At the same time, methods and tools for mixed-signal or system-level design still need maturing.  The concept of system-level design is being revolutionized as architectures like those required for IoT applications demand heterogeneous systems.

Attendees to DVCon U.S. will find ample opportunity to consider, debate, and compare both requirements and solutions that impact near term projects.

Tutorials and Papers

As part of its mission to provide a learning venue for designers and verification engineers, DVCon U.S. offers two full days of tutorials.  The presentations of the 12 tutorial sessions are divided between Monday and Thursday, separate from the rest of the technical program so they do not conflict and force attendees to make difficult attendance choices.

Accellera has a unique approach to putting together its technical program.  I am slightly paraphrasing this year’s Program Chair, Ambar Sarkar, by stating that DVCon U.S. lets the industry set the agenda, not the conference asking for papers on selected topics.  He told me that the basic question is: “Can a practicing engineer get new ideas and try to use them in his or her upcoming project?” For this reason, the call for papers asks only for abstracts and those that do not meet the request are eliminated.  After a further selection, the authors of the chosen abstracts are asked to submit a full paper.  Those papers are then grouped according to their common subject areas into sessions.  The sessions that emerge automatically reflect the latest trends in the industry.

The paper presentations during Tuesday and Wednesday take the majority of the conference’s time and form the technical backbone of the event.

Of the 127 papers submitted, 36 were chosen to be presented in full.  There will be 13 sessions covering the following areas: UVM, Design and Modeling, Low Power, SystemVerilog, Fault Analysis, Emulation, Mixed-Signal, Resource Management, and Formal Techniques.  Each session offers from 3 to 4 individual papers.

Posters

Poster presentations are selected in the same manner as papers.  A poster presentation is less formal but has the advantage of giving the author the opportunity to interact with a small audience and thus the learning process can be bilateral.  There have been occasions in the past when an abstract submitted as a poster is switched to an oral presentation with the consent of the author.  Such operation is possible because the submitting and selecting process is similar and thus the poster has already been judged as presenting an approach that will be useful to the attendees.

Keynote

This year’s keynote will be delivered by Wally Rhines, the 2015 recipient of the Phil Kaufman Award.  Wally is well known in the EDA industry for both his insight and his track record as the Chairman and CEO of Mentor Graphics.  The title of his address is Design Verification Challenges: Past, Present, and Future.  Dr. Rhines will review the history of each major phase of verification evolution and then concentrate on the challenges of newly emerging problems. While functional verification still dominates the effort, new requirements for security and safety are becoming more important and will ultimately involve challenges that could be more difficult than those we have faced in the past.

Panels: One Good and One Suspect

There are two panels on the conference schedule.  One panel: “Emulation + Static Verification Will Replace Simulation”, scheduled for Wednesday March 2nd at 1:30 in the afternoon looks at the near future verification methods.  Both emulation and static verification use has been increasing significantly.  May be the verification paradigm of the future is to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. Where does that leave RTL simulation? Between a rock and a hard place! Gate-level simulation is already marginalized to doing basic sanity checks. May be RTL simulation will follow. Or will it?

The other panel scheduled for 8:30 in the morning of the same day concerns me a lot.  The title is “Redefining ESL” and the description of the panel is taken from a blog that Brian Bailey, the panel moderator, published on September 24 of 2015.  You can read the blog here: http://semiengineering.com/what-esl-is-really-about/.

In the blog Brian holds the point of view that ESL is not a design flow, it is a verification flow, and it will not take off until the industry recognizes that. Only now are we beginning to define what ESL verification means, but is it too little, too late?  There are a few problems with the panels committee accepting this panel.  To begin with ESL is an outdated concept.  Today’s systems include much more than digital design.  Modern SoCs, even small ones like those fund in IoT applications, include analog, firmware, and MEMS blocks.  All of these are outside of the ESL definition and fall within the System Level Design (SLD) market.

The statement made by Brian that ESL would not be made viable by the introduction of viable High Level Synthesis (HLS) tools is simply false.  ESL verification became a valuable tool only when designers began to use HLS products to automatically derive RTL models from ESL descriptions in SystemVerilog or C/C++ even if HLS covered mostly algorithms expressed in something else besides Verilog, VHDL, or SystemC.

DVCon is the Primary Design and Verification Conference

Friday, February 20th, 2015

Gabe Moretti, Senior editor

DVCon United States opens on March 2nd and ends on March 5th.  If you have not yet made plans to attend and have something to do with developing ICs you should plan to attend.  The growth of this conference has been remarkable.

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera.  That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years.  Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.

The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages.  This year’s conference is the 27th and offers an expanded technical program.  In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year.  Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

The merger of OVI and VI produced significant changes, both for DVCon and for Accellera.  In 2001 DVCon boosted a more efficient organization, both for its technical program and for exhibits.  The source of papers offered for acceptance increased in scope as professionals outside of the Verilog and VHDL users communities became interested in presenting papers at the conference.

As Accellera grew and widened the scope of technical subject it handled, so DVCon increased the technical segments it covered.  First SystemC and shortly thereafter SystemVerilog provided interesting papers and Tutorials.  The verification aspect of the conference was enlivened with focus on UVM (Universal Verification Methodology), TLM (Transaction Level Modeling), testbench construction, and various approaches to testing, including formal techniques.

As the percentage of analog circuits increased in SoC, mixed languages and mixed signal design and verification also became a topic, both in papers and in Tutorials.  In fact one can quickly make a list of the most relevant issues current among electronics engineers by quickly reading the current conference program.

Yatin Trivedi, DVCon General Chair succinctly described the aim of DVCon..  ” DVCon continues to focus on serving the Design and Verification community. DVCon is a conference sponsored by Accellera, in order to promote the adoption of its standards and standards-based methodologies. From the days of exclusive focus on Verilog and VHDL, we have come a long way in including SystemVerilog, SystemC, UPF and UVM. As semiconductor IP became significant to our community of designers and verification engineers, the program has expanded its range of topics. However, our focus remains on design and verification.”

Accellera Systems Initiative UVM 1.2

Wednesday, June 25th, 2014

Gabe Moretti, Contributing Editor

In one of my blogs from this year’s DAC I mentioned the panel on UVM held during Accellera traditional Tuesday morning breakfast. The subject of UVM 1.2 was covered then. Now Accellera has officially announced the release of the new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. The new version includes enhanced messaging, improvements to the register layer and other features. UVM 1.2 and its reference implementation are available for download under Apache 2.0 open source license at www.accellera.org. During the recent DAC conference Accellera also held a tutorial on UVM 1.2.
“The UVM working group has achieved the goals of its charter to enhance SoC productivity throughout the industry,” said Tom Alsop, UVM Working Group co-chair. “We are proud to report that UVM 1.2 continues the work to define new features and improve quality of the reference implementation.”
UVM 1.2 is entering a three-month review period ending October 1, 2014 with a commitment to take the resulting updated UVM 1.2 standard to the IEEE. Users are encouraged to post comments and suggestions using the following link: http://forums.accellera.org/36-uvm-12-public-review.
During the panel discussion there were general praises for the new version although some of the panelists were a bit discouraged by the fact that the new standard is not compatible with the previous version. Unfortunately in building a standard is not possible to add significant new features and still maintain backward compatibility.

DVCon Europe Is The Wrong Venue

Wednesday, March 19th, 2014

DVCon USA, or should I call it DVCon SV for Silicon Valley, has just concluded another successful year.  The conference has grown significantly, and it compares favorably with other SV based conferences in our industry.  It is now a must attend event for all professionals involved in design verification.  On the heels of such growth Accellera Systems Initiative has announced the first European DVCon conference to be held this October 14 – 15 in Munich Germany.  I believe this is a suboptimal choice.

<b>Toward The Past, Not The Future</b>

Discussions among highly placed members of the Accellera board about starting a conference outside of the US have been going on for at least a couple of years, but the location most talked about was India, not Europe.

In spite of the attraction of Munich in October as a tourist destination, I have reservations as to the wisdom of the choice.  Europe already has a number of EDA and electronics conferences, and one more is not going to make much difference.   Europe is a mature market for the three key corporate powers within Accellera: Mentor, Synopsys, and Cadence. It is not clear what they expect to gain from the conference.

Accellera Technical Working Groups already enjoy good participation from European technologists.  What is needed is to involve representatives from the growth markets.  We need to know what they need, we already know what the US and European users need or think they need.

It would make much more sense to continue to pursue the India idea, although a modification of the venue to China instead of India would make sense.  I agree that the Europe location is easier to arrange.  There are European corporate members in Accellera who can offer support and organizational knowhow, but where is the drive to expand, both technically and economically?

I anticipate rebuttals from some of the board members pointing out that they have a working relationship with the ASP-DAC conference in Japan and thus Asia is serviced, albeit indirectly..  But Japan suffers from the same characteristics as Europe.  Japanese technologists already work within the Accellera Technical Working Groups, and Japan is a mature market for EDA companies.

Growth needs new opportunities and new ideas, not recognition of past and present contributions, no matter how substantial and noteworthy they might have been.  So Accellera board members enjoy your liter of new beer this fall, but think about how many new corporate and technical WG members you could get from locating a conference in China.