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ESDA CEO Outlook Panel, not a Cause for Celebration

Tuesday, April 25th, 2017

Gabe Moretti, Senior Editor

About two weeks ago the ESD Alliance held its 2017 CEO Outlook Panel.  The panel used to be a yearly event for EDAC, the precursor of the ESD Alliance, but had not been held for a few years since.

I did not have the opportunity to attend the panel in person and was looking forward to read the entire transcript on the ESDA site.  But there is no transcript.  There is a picture of the panelists with Ed Sperling as the moderator, and a brief video showing introductory remarks from each of the panelists.

Unfortunately, the introductory remarks could have been delivered by a set of industry cheerleaders, since there was really no depth in them.  You can guess the contents: greater need for silicon, IoT and IIoT (Industrial IoT) are the future.  Lip-Bu Tan did say something interesting by addressing data architecture within the IIoT.  Too many articles have been written about the IoT hardware architecture and I have found almost nothing that talks about the data architecture.  Lip-Bu emphasized the need for local computational and decision making capability, thus limiting the need to transfer large amount of data up in the hierarchy of the system.  Given the complex connectivity of a IoT system, where everything is potentially connected to everything else, security would be a major concern should the need to transfer a large amount of information arise.  The smaller the amount of data transfer, the higher the security.

What Lip-Bu did not say, but is implied, is the need for distributed intelligence in the system with application specific hardware playing a greater role.  It is back to the future.  ASIC once again will step to the forefront replacing software based system running on general purpose hardware.

Wally Rhines noted that our industry economics are back at the levels of six years ago in spite of the significant consolidation of our customer base.  It is called recovery, and our industry has had less of a recovery than most other industries.

The consolidation issue points out the real problem of the EDA industry.  We sell tools used in the design and development of a product, not its manufacturing.  Manufacturing volume means nothing to the EDA bottom line.  Fewer “makers” means fewer “tools needed”.

Mentor is now part of one of its customers, so does such consolidation matter to Wally?  I hear of course that Mentor will continue to do business in an independent manner, and that will be true unless and until a conflict of interest ensues.  Will Mentor sell its best tools to companies directly competing with Siemens in a specific, competitive, market?

Simon Segers of ARM was also part of the panel.  If he said something important as a result of now working for SoftBank, you could not have guessed it from his introductory remarks either.  He just repeated Aart De Geus observation about the world needing more silicon.  It has been clear since the acquisition that SoftBank other captive industries need more silicon and more IP cores, the reason for the acquisition!  ARM will expertly create whatever SoftBank needs and will market what it creates to the outside world.  The other way around will not happen, at least not in any important way.

Speaking as the scientist that he is Aart pointed out that as algorithms’ complexity increases the need for computational capability increases as well, thus the need for more silicon.  It is an assumption that increased silicon production means increased EDA revenue.  This is a fallacy, since EDA revenues are realized at the front end of the project and do not grow with product volume!  The amount of EDA products that are used in wafer production and testing is small in comparison to the tools used to design and test before production.

There is also a significant difference in the revenue generated by different types of silicon.  A 90 nm device requires less up-front investment in tools than a 10nm device.  And there will be much more of the former than the latter type.

I think that reviving the CEO Panel is a good thing.  It shows, at least, that accepted leaders of the EDA industry are willing to appear in public and deliver statements without fear of sounding irrelevant.  And the lack of a full transcript, given the high level of professionalism now in the ESDA, must mean that nothing worthy of greater analysis was said during the panel.

Interview with Pim Tuyls, President and CEO of Intrinsic-ID

Tuesday, October 4th, 2016

Gabe Moretti, Senior Editor

After the article on security published last week, I continued the conversation with more corporations.  The Apple vs. FBI case showed that the stakes are high and the debate is heated.  Privacy is important, not only for guarding sensitive information but for also ensuring functionality in our digital world.

I asked Pim Tuyls his impressions on security in electronics systems.


“Often, privacy is equated with security. However, ‘integrity’, is often the more important issue. This is especially true with the Internet of Things (IoT) and autonomous systems, which rely on the inputs they receive to operate effectively.    If these inputs are not secure, how can they be trusted?  Researchers have already tricked sensors of semi-autonomous cars with imaginary objects on the road, triggering emergency braking actions.  Counterfeit sensors are already on the market.

Engineers have built in redundancy and ‘common-sense’ rules to help ensure input integrity. However, such mechanisms were built primarily for reliability, not for security. So something else is needed. Looking at the data itself is not enough. Integrity needs to be built into sensors and, more generally, all end-points.”

Chip Design: Are there ways you think could be effective in increasing security?


“One way to do this is to append a Message Authentication Code (MAC) to each piece of data. This is essentially a short piece of information that authenticates a message or confirms that the message came from the claimed sender (its authenticity) and has not been changed in transit (its integrity). To protect against replay attacks the message is augmented with a timestamp or counter before the MAC is calculated.  Another approach to implement a MAC is based on hash functions (HMAC or Hash-based message authentication code). Hash functions such as the SHA-2 family are well-known and widely supported cryptographic primitives with efficient and compact implementation.”

Chip Design: These approaches sound easy but there are reasons they are not widely adopted?


“First, even though an algorithm like HMAC is efficient and compact, it may still be too high of a burden on the tiny microcontrollers and sensors that are the nerves of a complex system.  Authenticating every piece of data naturally takes up resources such as processing, memory and power.  In some cases, like in-vitro medical sensors, any reduction in battery life is not acceptable. Tiny sensor modules often do not have any processing capabilities. In automotive, due to the sheer number of sensors and controllers, costs cannot be increased.”

Chip Design: It is true that many IoT devices are very cost sensitive, I said, however, over recent years there is an increasing use of more powerful, 32-bit, often ARM- based microcontrollers. Many of these now come with basic security features like crypto accelerators and memory management. So some of the issues that prevent adoption of security are quickly being eroded.

Pim continued:

“A second obstacle relates to the complex logistics of configuring such a system. HMAC relies on a secret key that is shared between the sensor and the host.  Ensuring that each sensor has a unique key and that the key is kept secret via a centralized approach creates a single point of failure and introduces large liabilities for the party that manages the keys.”

Chip Design: What could be a cost-effective solution?

Pim concluded:

“A new solution to all these issues is based on SRAM Physical Unclonable Functions (PUFs). An SRAM PUF can reliably extract a unique key from a standard SRAM circuit on a standard microcontroller or smart sensor. The key is determined by tiny manufacturing differences unique to each chip. There is no central point of failure and no liability for key loss at the manufacturer.  Furthermore, as nothing is programmed into the chip, the key cannot even be extracted through reverse engineering or other chip-level attacks.

Of course adapting a new security paradigm is not something that should be done overnight. OEMs and their suppliers are rightly taking a cautious approach. After all, the vehicle that is now being designed will still be on the road in 25 years. For industrial and medical systems, the lifecycle of a product may even be longer.

Still, with technologies like SRAM PUF the ingredients are in place to introduce the next level of security and integrity, and pave the road for fully autonomous systems. Using such technologies will not only help to enhance privacy but will also ensure a higher level of information integrity.”

This brought me back to the article where a solution using PUF was mentioned.

Hardware Based Security

Friday, August 5th, 2016

Gabe Moretti, Senior Editor

If there is one thing that is obvious about the IoT market it is that security is essential.  IoT applications will be, if they are not already, invasive to the life of their users and the privacy of each individual must be preserved.  The European Union has stricter privacy laws than the US, but even in the US privacy is valued and protective.

Intrinsic-ID has published a white paper “SRAM PUF: The Secure Silicon Fingerprint” that you can read in the Whitepapers section of this emag, or you can go to and read it under the “Papers” pull down.

For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology that was making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ranging from tiny sensors and microcontrollers to high performance Field-Programmable Gate Arrays (FPGAs) and secure elements where they protect financial transactions, user privacy, and military secrets.

Intrinsic-ID goal in publishing this paper is to show that SRAM PUF is a mature technology for embedded authentication. The behavior of an SRAM cell depends on the difference of the threshold voltages of its transistors. Even the smallest differences will be amplified and push the SRAM cell into one of two stable states. Its PUF behavior is therefore much more stable than the underlying threshold voltages, making it the most straightforward and most stable way to use the threshold voltages to build an identifier.

It turns out that every SRAM cell has its own preferred state every time the SRAM is powered resulting from the random differences in the threshold voltages. This preference is independent from the preference of the neighboring cells and independent of the location of the cell on the chip or on the wafer.

Hence an SRAM region yields a unique and random pattern of 0’s and 1’s. This pattern can be called an SRAM fingerprint since it is unique per SRAM and hence per chip. It can be used as a PUF. Keys that are derived from the SRAM PUF are not stored ‘on the chip’ but they are extracted ‘from the chip’, only when they are needed. In that way they are only present in the chip during a very short time window. When the SRAM is not powered there is no key present on the chip making the solution very secure.

Intrinsic-ID has bundled error correction, randomness extraction, security countermeasures and anti-aging techniques into a product called Quiddikey. This product extracts cryptographic keys from the SRAM PUF in a very secure manner and is available as Hardware IP (netlist), firmware (ANSI C Code), or a combination of these.

The hardware IP is small and fast – around 15K gates / 100K cycles – and connects to common interconnects like AMBA AHB, APB as well as proprietary interfaces. A Built-In Self-Test (BIST) and health checks are included in the logic. Since it is pure digital, single clock logic it synthesizes readily to any technology.  Software reference implementations start from 10KB of code and are available for major platforms like ARM, ARC, Intel and MIPS. Software implementations can be used to add PUF technology to existing products by a firmware upgrade.

I will deal with security issues in more depth in September.  In the mean time the Intrisic-ID white paper is worth your attention

Reverse Acquisition

Monday, July 25th, 2016

Gabe Moretti, Senior Editor

It has been now one week since SoftBank of Japan has announced its intention to acquire ARM for a little over $32 billion in cash, an eye popping 43% premium from the stock price before the announcement.  As I have remarked in my previous blog:“ The ARM – SoftBank Deal : Heart Before Mind) the financials do not make sense, but, after a week of consideration and after reading Junko Yoshida’s interview of Masayoshi Son, SoftBank CEO, I can see how it makes strategic sense.  This is of course my interpretation, not something SoftBank would ever confirm.

I started by considering how Japan has not been able to recover from its industrial near collapse, in spite of its use of every financial tool, both conventional and somewhat unconventional.  There is only one thing left to do: get foreign companies, especially those leading in their fields, to invest in Japanese companies.  But of course, there have been no takers. What to do next: buy one!  And that is what SoftBank has done.

I should have trusted my intuition immediately.  Looking at the title of my blog I wrote ARM- SoftBank Deal.  It should in fact have been SoftBank – ARM deal, since SoftBank is the acquiring party.  Here is what is actually happening.

SoftBank is “lending” ARM $32 billion to “purchase” SoftBank.  Masayoshi Son has stated: “I may choose to become ARM’s Chairman of the Board”.  He has also stated that the reason for the purchase is to use ARM products within all of the fiscal deals SoftBank is involved in at this point like: Vodaphone Japan, Alibaba, and TaoBao.  Any entry in new markets is analysts speculation.

Yoshida reports Son stating: ““ARM will become central to SoftBank’s core business in three, five and 10 years’ time,” he said.  Note he did not say that ARM will provide new markets, only that it will strengthen existing ones.  And since ARM will be a wholly owned division of SoftBank, there will be no regulations compelling SoftBank to divulge operational details of ARM that it does not choose to make public.  Thus much of what SoftBank will do under the ARM cover will remain private.

Should we expect another such move from Japan,Inc.?  I will be watching the financial news carefully for a while now.

The ARM – Softbank Deal: Heart Before Mind

Tuesday, July 19th, 2016

Gabe Moretti, Senior Editor

If you happen to hold ARM stock, congratulation, you are likely to make a nice profit on your investment.  SoftBank, a Japanese company with diversifies interests, including Internet provider, has offered to purchase ARM for cash by tendering $32.4 billion dollars.  SoftBank is a large company whose latest financial result show that it made a profit of $9.82 before interest payments and tax obligations.

ARM, on the other hand, reported for 2015 fiscal year revenue of $1.488.6 billion with a profit of $414.8 million and an operating margin of 42%.  This is a very healthy operating margin, showing a remarkable efficiency by all aspects of the company.  So, there is little to improve in the way ARM operates.

What seems logical, then is that SoftBank expects a significant increase in ARM revenue after the acquisition, or an effect on its profit due to ARM’s impact on other parts of the company.  ARM profit for 2015 were 414.8 million British sterling and the revenue in sterling was 968.3 million for a ratio of 42.8%.  Let’s assume that SoftBank instead invested all of the $32.4 billion and obtained a 5% return or $1.62 billion per year.  To obtain the same result from the ARM acquisition it would mean that ARM must generate a profit of 3.9 times what it generated in 2015.  This is a very large increase since if we assume that all other financial ratios stay the same revenue would have to be a little over $5.5 billion. Yet, using the growth of 15% realized between 2014 an2015 for every year between 2015 and 2020 we “only” achieve a $2,913.6 billion mark.  And keeping the growth ratio constant as revenue increase gets harder and harder since it means a large increase every year.

So the numbers do not make sense to me.  I can believe that ARM could be worth $16 billion, but not twice as much.  And here is another observation.  I have read in many publications that financial analysts expect the IoT market to be $20 billion by 2020.  Assuming that the SoftBank investment, net of interest charges, returns 5% per year in 2020, it would mean that ARM’s revenue would be $5.5 billion or over 25% of TAM (Total Available Market).  This, I consider impossible to achieve, simply because the IoT market will be price sensitive, thus opening ARM to competition by other companies offering competitive microcontrollers.  SoftBank cannot possibly believe that Intel will go away, or that every person will own three cell phones each, or that Google will use only ARM processors in its offerings, or even that IP companies like Cadence and Synopsys will decide to ignore the IoT market.

I am afraid that the acquisition marks the end of ARM as we know it.  It will be squeezed for revenue and profit like it has never been before and the quality of its products will suffer.

Synopsys’ Relaunched ARC Is Not The Answer

Wednesday, October 14th, 2015

Gabe Moretti, Senior Editor

During the month of September Synopsys spent considerable marketing resources relaunching its ARC processor family of products by leveraging the IoT.  First on September 10 it published a release announcing two additional versions of the ARC EM family of deeply embedded DSP cores.  Then on September 15 the company held a free one-day ARC Processor Summit in Santa Clara and on September 22 issued another press release about its involvement in IoT again mentioning the embARC Open Software Platform and ARC Access Program.  It is not clear that ARC will fare any better in the market after this effort than it did in the past.


Almost ten years ago a company called ARC International LTD designed and developed a RISC processor called Argonaut RISC Core.  Its architecture has roots in the Super FX chip for the Super Nintendo Entertainment System.  In 2009 Virage Logic purchased ARC International.  Virage specialized in embedded test systems and was acquired by Synopsys in 2010.  This is how Synopsys became the owner of the ARC architecture, although it was just interested in the embedded test technology.

Since that acquisition ARC has seen various developments that produced five product families all within the DesignWare group.  Financial success of the ARC family has been modest, especially when compared within the much more popular product families in the company.  The EM family is one of the five product families where the two new products reside.  During this year’s DVCon, at the beginning of March I had an interview with Joachim Kunkel, Sr. Vice President and General Manager of the Solutions Group at Synopsys who is responsible among other things of the IP products.  We talked about the ARC family and how Synopsys had not yet found a way to efficiently use this core.  We agreed that IoT applications could benefit from such an IP especially if well integrated with other DesignWare pieces and security software.

The Implementation

I think that the ARC family will never play a significant part in Synopsys revenue generation, even after this last marketing effort.

It seems clear to me that the IoT strategy is built on more viable corporate resources than just the ARC processor.  The two new cores are the EM9D and EM11D which implement an enhanced version of the ARCv2DSP instruction set architecture, combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimizing power consumption.  Synopsys claims that the cores are from 3 to 5 times more efficient than the two previous similar cores, but the press release specifically avoids comparison with similar devices from other vendors.

When I read the data sheets of devices from possible competitors I appreciate the wisdom to avoid direct comparison.  Although the engineering work to produce the two new cores seems quite good, there is only so much that can be done with a ten years old architecture.  ARC becomes valuable only if sold as part of a sub-system that integrates other Synopsys IP and security products owned by the company.

It is also clear that those other resources will generate more revenue for Synopsys when integrated with other DSP processors from ARM, Intel, and may be Apple or even Cadence.  ARC has been neglected for too long to be competitive by itself, especially when considering the IoT market.  ARC is best used at the terminals or data acquisition nodes.  Such nodes are highly specialized, small, and above all very price sensitive.  A variation of few cents makes the difference between adoption or not.  This is not a market Synopsys is comfortable with.  Synopsys prefers to control by offering the best solution at a price it finds acceptable.


The ARC world will remain small.  Synopsys mark on the IoT will possibly be substantial but certainly not because of ARC.

Gary Smith’s DAC presentation: The Changing Landscape

Friday, June 26th, 2015

Gabe Moretti, Senior Editor

Since a couple of weeks have passed I have had time to think about the contents of the Sunday evening presentation by Gary Smith.  Gary touched many subjects but two in particular gave me reason to ponder.  The first one was his comment on the IP industry and the second his view on Synopsys expansion.

The IP Industry

Gary stated that revenue for IP products will first level off and then diminish in the period up to 2019.  This statement generated incredulous response from the audience.  In the time set aside for questions Gary stated that the reason for the decline was the market saturation for products like Synopsys DesignWare.

He said that small IP modules were now commodities that are free, or practically free, and that the only source of IP revenue will be IP subsystems.  By itself the statement is true, but I think that Gary missed the larger picture.  IP subsystems are growing in sophistication and now contain both hardware and firmware modules.  Their complexity will increase, not decrease, and with it the price they can command.  The projected expansion of IoT products also means a growing use of IP subsystems, thus a very large growth in the number of licenses sold.

In addition the sophistication of the subsystems require more powerful development tools to integrate the IP and debug the final system.  ARM, for example has just introduced a very sophisticated development environment.  The new IP tooling suite comprises Socrates DE, CoreSight Creator and CoreLink Creator. Additionally, CoreLink Creator will easily configure and help implement the new CoreLink NIC-450 Network Interconnect, the follow-on to the widely-adopted CoreLink NIC-400.  See my article at:

How is the revenue generated by this new tool, and those likely to appear on the market by competitors, to be counted?  Clearly the revenue would not exist if the IP was not purchased and used.  So, I think, tools specifically used for IP, should be counted in the IP market, not in the general EDA tools markets.  In addition the firmware sold with or for IP should not be counted in the embedded software column, but in the IP column.  IP revenue will grow, it is just a matter how it will be counted.

Synopsys’s Growth

Gary observed that Synopsys was growing through acquisitions in niche markets with the intent to dominate those markets.  I think this view is too narrow.  To be sure Synopsys acquires companies that have a significant opportunity to grow, but the reason for the acquisitions is not “just” diversification.  If one steps back and looks at the system level, and not just at the electronic hardware level, one finds, or at least I find, that Synopsys is looking at the requirements of systems in  the near future and is obtaining the tools to be able to satisfy them as a company.  Security is an important especially with respect to software attacks.  The acquisition of Codenomicon addresses the robustness of developed software.  The earlier acquisition of Coverity is fundamentally in the same direction.  Gary is correct that both acquisitions bring Synopsys in the larger market of software development outside of EDA, but they also strengthen the corporate position within EDA.  The same can be said of the Optical Solution Group grown entirely by acquisition of non EDA companies.  My point is that Synopsys is becoming a true system company, not “just” an EDA company.

Cadence Introduces Indago Debug Platform

Tuesday, April 28th, 2015

Gabe Moretti, Senior Editor

Cadence Design Systems, Inc. announced the Cadence Indago Debug Platform, a new debugging solution which the company claims it reduces the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods.

Cadence chose to put the accent on the second syllable.  Personally I think that the accent on the first syllable would give more verve to the name, while the accent on the second makes it more laid back.  But I do need to find some drawbacks in the product!

The patented root-cause analysis technology in the Indago Debug Platform filters unneeded data that would usually be needed to go to the source of a single bug to resolve the cause of all related bugs.  Current debug methodologies used by designers require multiple simulation iterations to incrementally extract data points that ultimately point to the source of the bug. The technology in the Indago Debug Platform can reduce the time necessary to resolve schedule-impacting bugs significantly using a common set of resources that enable a suite of commercial and user-created Apps that automate the analysis of data from multiple verification engines and multiple vendors.

“Leading-edge verification projects create terabytes of data every day, making debug a big data problem for semiconductor and system companies,” said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.  “With the Indago Debug Platform, Cadence helps solve this problem by automating the process of finding the root cause for a bug. For the first time, engineers can have a collaborative environment across multiple verification engines that both reduces the time to solve the discovered bug and the root cause for other bugs that may be buried in the data.”

In addition to the Indago Debug Platform, Cadence also announced three debugging apps that plug into the platform and can be used with other verification tools to provide an integrated and synchronized debug solution for testbench, verification IP (VIP), and hardware/software debug for system-on-chip (SoC) designs.

The Indago Debug Platform and debugging apps are part of the comprehensive Cadence System Development Suite and are currently available for early adopters. General availability is expected by June 2015.

With a unified debug platform and the debug apps, the Indago Debug Platform enables multiple engineering specialists from design, testbench, embedded software and protocol verification to operate as a team to resolve SoC bugs. The three debug apps are:

- Indago DebugAnalyzer:  Extends root-cause analysis from etestbench (IEEE 1647) to SystemVerilog (IEEE 1800)and increases performance by up to 10X

- Indago Embedded Software Debug: Resolves bugs associated with embedded software applications by synchronizing software and hardware source code debug

- Indago Protocol Debug:  Visualizes advanced protocols such as DDR4, ARM AMBA AXI and ACE using Cadence VIP.

IP Components Are EDA Tools

Friday, January 9th, 2015

Gabe Moretti, Senior Editor

It has been just about 25 years since the first IP product was licensed and yet there are still questions about the true nature of the IP industry.  A few years ago EDAC started providing figures for IP revenue, and that created a debate that to some extent continues today.  Is an IP company an EDA company?  Some say yes and some strongly object and prefer to define an IP company as a fabless semiconductor company.  Is there a correct definition of the industry that creates IP?  And which IP are we talking about?  EDAC is looking only at hardware IP, but of course there are many software IP products available.  What is IP?  The name itself is not very specific.  IP stands for Intellectual Property, but that covers anything that can be copyrighted, patented, or otherwise claimed to be property that cannot be freely copied, sold, or used without express permission from its creator.  It was not the intention of the creator of the term to cover all those items, but then marketing is a difficult if imprecise, job.

So to make things easier, let’s discuss only about the IP components representing hardware that are used by hardware designers in the design and development of hardware.  Are the producers and vendors of such products EDA companies?  To be sure some EDA companies develop and sell IP.  Cadence, Mentor, and Synopsys call themselves EDA companies and all generate revenue from licensing IP products.  ARM, the leading IP company, sells development software for its products that is just as sophisticated as tools sold by EDA companies, so is ARM an EDA company?

I would like to look at IP in a different light, a point of view I share with Lucio Lanza.  IP components are used by designers in the design and development of electronic products.  The EDA industry’s purpose is to develop and market tools used by designers to design and develop electronic products.  Ergo, IP is an EDA tool.  In fact engineers do not just integrate IP components in their designs.  They use IP in making tradeoff judgments regarding architecture, performance, development cost, and ultimately price of the product they are working on.  IP is indeed an EDA tool, so EDAC is correct in counting the revenue as an EDA industry revenue.

There is also a practical aspect to the argument.  One cannot separate IP revenue from the overall revenues of Cadence, Mentor, or Synopsys, just to take the big three into consideration, without those companies deciding to account for IP revenues as a separate profit center.  And why should they if IP is the same as EDA tools?

The Divorce That Never Happened

Monday, October 6th, 2014

Gabe Moretti, Senior Editor

Last week ARM and Synopsys jointly announced a new agreement that allows Synopsys an early access to a wide range of ARM product families in order to tune the Synopsys tools to the requirements engineers will face when developing systems containing those IP cores.

The multi-year subscription agreement expands Synopsys’ access to a broad range of ARM intellectual property (IP) and related technologies to enable optimization of Synopsys tools and methodologies for ARM-based system-on-chips (SoCs). Through this agreement, Synopsys has pre-production access to ARM Cortex processors for the ARMv8-A and ARMv7-A architectures, ARM Mali graphics processors, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP for implementation acceleration. Building on more than 20 years of collaboration as well as the August 2012 license agreement between the companies for ARMv7-A processors and related IP, this new agreement allows Synopsys to further optimize its design flows and tools for ARM-based SoCs, enabling designers to meet their power, performance and area goals, while reducing cost and time-to-market.

It was only four years ago that the rumor was that following Synopsys acquisition of Virage Logic and its ARC family of processors there would not be any more room for ARM and Synopsys to work together.   I was told that Cadence would replace Synopsys as the preferred EDA vendor at ARM.  I was instructed on the short sighted move Synopsys had made by entering the MCU market with a family of products that had never been competitive in the market.  And I was told that Synopsys would have to scrap the ARC family of products and eat humble pie in order to ever see another dollar from ARM.

At the time I had very few ammunitions to combat those positions.  But I knew Synopsys and I was sure that some significant due diligence had been done before expanding there presence in the design for test market with established IP products.   And it did not make sense to me that Synopsys would let an “accident” spoil its relationship with ARM.  The result was that I did not join the ranks of those prophesying imminent ruin for Synopsys,

Or even an open marketing war between ARM and Synopsys.  I did not, to be fair, also not openly contest those rumors, coming as they were, from individuals who are frequently, “in the know”.

If there ever were dirty linens involved, they were cleaned privately: after all ARM knew where ARC processors fit in the market, and had never spent much effort in defending its market from Virage Logic.  So during all the ensuing years relationships between ARM and Synopsys have continued to be positive, and, just in time for ARM TechCon we are given the strongest possible assurance that the two companies are making money together by leveraging each other’s technology.

The multi-year subscription agreement  expands Synopsys’ access to a broad range of ARM intellectual property (IP) and related technologies to enable optimization of Synopsys tools and methodologies for ARM-based system-on-chips (SoCs). Through this agreement, Synopsys has pre-production access to ARM Cortex processors for the ARMv8-A and ARMv7-A architectures, ARM Mali graphics processors, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP for implementation acceleration. Building on more than 20 years of collaboration as well as the August 2012 license agreement between the companies for ARMv7-A processors and related IP, this new agreement allows Synopsys to further optimize its design flows and tools for ARM-based SoCs, enabling designers to meet their power, performance and area goals, while reducing cost and time-to-market.

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