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DVCon Is a Must Attend Conference for Verification and Design Engineers

Monday, February 13th, 2017

Gabe Moretti, Senior Editor

Dennis Brophy, Chair of this year’s DVCon said that “The 2017 Design and Verification Conference and Exhibition U.S. The conference will offer attendees a comprehensive selection of 39 papers, 9 tutorials, 19 posters, 2 panels, a special session on Functional Verification Industry Trends, and a keynote address by Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group at Cadence.”

DVCon is   sponsored by Accellera Systems Initiative, DVCon U.S. will be held February 27-March 2, 2017 at the DoubleTree Hotel in San Jose, California.

DVCon was initially sponsored by VHDL International and Open Verilog International; but its growth really started after the two organizations merged  to form Accelera which was renames Accellera Systems Initiative during its merger with Open SystemC Initiative.  It seems that every EDA organization now-a-days needs the word “systems” in its name.  As they are afraid to be seen to be of lesser importance without making very sure that everyone knows they are aware of the exitance of systems.

DVCon is now a truly international conference holding events not only in the US but also in Europe, India and, for the first time this year, in China.

The aim of Accellera is to build and serve a community of professionals who focus on development and verification of hardware systems, with the awareness that software role in system design is growing rapidly.  Dennis Brophy observed that “Coming together as a community is fostered by the DVCon Expo. The bigger and better exposition will run from Monday evening to Wednesday evening. See the program for specific opening and closing times. The Expo is a great place to catch up with commercial vendors and learn the latest in product developments. It is also great to connect with colleagues and exchange and share information and ideas. Join us for the DVCon U.S. 2017 “Booth Crawl” where after visiting select exhibitors you will be automatically entered for a lucky draw.”

Although the titles of the papers presented in the technical conference focus on EDA technologies, the impact of the papers deal with application areas diverse from automotive to communications, from the use of MEMS and FPGA in system design, from could computing to rf.

“DVCon has long been the technical and social highlight of the year for design and verification engineers,” stated Tom Fitzpatrick, DVCon U.S. 2017 Technical Program Chair.  “Through the hard work of a large team of dedicated reviewers, we have chosen the best of over one hundred submitted abstracts from deeply knowledgeable colleagues within the industry to help attendees learn how to improve their verification efforts. We also have two days of extended tutorials where attendees can get an in-depth look at the cutting edge of verification, not to mention the Exhibit Floor where over 30 companies will be demonstrating their latest tools and technologies.  In between, there are plenty of opportunities to network, relax and take advantage of a fun and welcoming atmosphere where attendees can reconnect with old friends and former colleagues or make new friends and contacts. The value of DVCon goes well beyond the wealth of information found in the Proceedings. Being there makes all the difference.”

Dennis Brophy added that on Monday February 27th there will be a presentation covering the Portable Stimulus work being done under Accellera sponsorship.  The working group has made significant progress toward defining what it is and how it works.  The goal is to have the Board of Accellera to authorize a ballot to make the result an industry standard and to further take it to the IEEE to complete the standardization owkr.

As has happened last year the exhibit space was quickly filled by vendor who understood the advantage of talking with technologists who specialize in verification and design of complex systems.

Devgan’s keynote, “Tomorrow’s Verification Today” will review the latest trends which are redefining verification from IP to System-level with an increasingly application-specific set of demands for hardware and software development. Over the past decade, verification complexity and demands on engineering teams have continued to raise rapidly. However, the supporting automation tools and flows have been only improving incrementally, resulting in a verification gap. It is time to redefine how verification should be approached to accelerate innovation in the next decade.  In his presentation, Dr. Devgan will review the latest trends which are redefining verification from IP to System-level, with an increasingly application-specific set of demands changing the landscape for hardware and software development. The keynote will be delivered on Tuesday, February 28

On the same day from 1:30-2:30pm in the Oak/Fir Ballroom the conference will offer a special session with Harry Foster, Chief Scientist for Mentor Graphics’ Design Verification Technology Division.  Foster has been asked to present “Trends in Functional Verification: A 2016 Industry Study” based on the Wilson Research Group’s 2016 study. The findings from the 2016 study provide invaluable insight into the state of today’s electronics industry. It will be held on Tuesday, February 28 from 10:30-11:00am in the Fir Ballroom.

Two full days of in-depth tutorials: Accellera Day with three tutorials on Monday and sponsored tutorials on Thursday.  There are also many technical papers and posters and two intriguing panels.

There will be plenty of networking opportunities, especially during the exhibition.  There will be a booth crawl on Monday, February 27 from 5:00-7:00pm and receptions both Tuesday and Wednesday in the exhibit hall.  Exhibits will be open Tuesday from 5:00-7:00pm and Wednesday and Thursday from 2:30-6:00p

The awards for Best Paper and Best Poster will be presented at the beginning of the reception on Wednesday.  For the complete DVCon U.S. 2017 schedule, including a list of sessions, tutorials, sponsored luncheons and events, visit www.dvcon.org.

DVCon is the Primary Design and Verification Conference

Friday, February 20th, 2015

Gabe Moretti, Senior editor

DVCon United States opens on March 2nd and ends on March 5th.  If you have not yet made plans to attend and have something to do with developing ICs you should plan to attend.  The growth of this conference has been remarkable.

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera.  That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years.  Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.

The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages.  This year’s conference is the 27th and offers an expanded technical program.  In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year.  Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

The merger of OVI and VI produced significant changes, both for DVCon and for Accellera.  In 2001 DVCon boosted a more efficient organization, both for its technical program and for exhibits.  The source of papers offered for acceptance increased in scope as professionals outside of the Verilog and VHDL users communities became interested in presenting papers at the conference.

As Accellera grew and widened the scope of technical subject it handled, so DVCon increased the technical segments it covered.  First SystemC and shortly thereafter SystemVerilog provided interesting papers and Tutorials.  The verification aspect of the conference was enlivened with focus on UVM (Universal Verification Methodology), TLM (Transaction Level Modeling), testbench construction, and various approaches to testing, including formal techniques.

As the percentage of analog circuits increased in SoC, mixed languages and mixed signal design and verification also became a topic, both in papers and in Tutorials.  In fact one can quickly make a list of the most relevant issues current among electronics engineers by quickly reading the current conference program.

Yatin Trivedi, DVCon General Chair succinctly described the aim of DVCon..  ” DVCon continues to focus on serving the Design and Verification community. DVCon is a conference sponsored by Accellera, in order to promote the adoption of its standards and standards-based methodologies. From the days of exclusive focus on Verilog and VHDL, we have come a long way in including SystemVerilog, SystemC, UPF and UVM. As semiconductor IP became significant to our community of designers and verification engineers, the program has expanded its range of topics. However, our focus remains on design and verification.”