Part of the  

Chip Design Magazine

  Network

About  |  Contact

Posts Tagged ‘DVCon’

Portable Stimulus

Thursday, March 23rd, 2017

Gabe Moretti, Senior Editor

Portable Stimulus (PS) is not a new sex toy, and is not an Executable Specification either.  So what is it?  It is a method, or rather it will be once the work is finished to define inputs independently from the verification tool used.

As the complexity of a system increases, the cost of its functional verification increases at a more rapid pace.   Verification engineers must consider not only wanted scenarios but also erroneous one.  Increased complexity increases the number of unwanted scenarios.  To perform all the required tests, engineers use different tools, including logic simulation, accelerators and emulators, and FPGA prototyping tools as well.  To transport a test from one tool to another is a very time consuming job, which is also prone to errors.  The reason is simple.  Not only each different class of tools uses different syntax, in some cases it also uses different semantics.

The Accellera System Initiative, known commonly as simply Accellera is working on a solution.  It formed a Working Group to develop a way to define tests in a way that is independent of the tool used to perform the verification.  The group, made up of engineers and not of markting professionals, chose as its name what they are supposed to deliver, a Portable Stimulus since the verification tests are made up of stimuli to the device under test (DUT) and the stimuli will be portable among verification tools.

Adnan Hamid, CEO of Breker, gave me a demo at DVCon US this year.  Their product is trying to solve the same problem, but the standard being developed will only be similar, that is based on the same concept.  Both will be a descriptive language, Breker based on SystemC and PS based on SystemVerilog, but the approach the same.  The verification team develops a directed network where each node represents a test.  The Accellera work must, of course, be vendor independent, so their work is more complex.  The figure below may give you an idea of the complexity.

Once the working group is finished, and they expect to be finished no later than the end of 2017, each EDA vendor could then develop a generator that will translate the test described in PS language into the appropriate string of commands and stimuli required to actually perform the test with the tool in question.

The approach, of course, is such that the product of the Accellera work can then be easily submitted to the IEEE for standardization, since it will obey the IEEE requirements for standardization.

My question is: What about Formal Verification?  I believe that it would be possible to derive assertions from the PS language.  If this can be done it would be a wonderful result for the industry.  An IP vendor, for example, will then be able to provide only one definition of the test used to verify the IP, and the customer will be able to readily use it no matter which tool is appropriate at the time of acceptance and integration of the IP.

DVCon is a Worldwide Conference

Wednesday, December 21st, 2016

Gabe Moretti, Senior Editor

The DVCon conference has now solid traditions not only in the USA but also in Europe, India, and next year will start flowering in China.

DVCon U.S.

The conference will be held February 27 – March 2, 2017 at the DoubleTree in San Jose, California. Early registration was open and the program is available on line at  https://dvcon.org. “DVCon U.S. 2017 planning is taking shape,” commented Dennis Brophy, DVCon U.S. General Chair. “We look forward to a compelling and in-depth technical program full of engaging content that practicing design and verification engineers, managers and EDA tool suppliers have come to depend on from DVCon.” The four-day program offers attendees an Expo, two exciting standards-focused panels and numerous informative papers, tutorials and posters to choose from. Accellera Day starts the conference on Monday and will devote the entire morning to a tutorial on Accellera’s emerging Portable Stimulus standard titled “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” with two afternoon tutorials: “SystemC Design and Verification – Solidifying the Abstraction above RTL” and “Introducing IEEE P1800.2 – The Next Step for UVM.”

DVCon India

This important technical event in India was held in Bangalore in September with almost 440 attendees over the two-day event. There were local start-ups participating and exhibiting for the first time, further demonstrating the local focus and interest in each conference. “DVCon India rightly promotes the four C’s: connect, contribute, collaborate, and celebrate,” stated Gaurav Jalan, DVCon India General Chair. The two-day event was inaugurated with a traditional lamp-lighting ceremony and welcome remarks by Jalan. Dr. Walden Rhines, Chairman and CEO of Mentor Graphics, and Professor Kamakoti Veezhinathan, Indian Institute of Technology Madras, delivered the keynotes.

DVCon Europe

As in previous years the conference was held in Munich, Germany. Held in October it enjoyed an increase in attendance of 20% over the previous year. Attendees of the two-day conference included representatives from 93 companies and organizations from 25 countries. Insightful keynotes were delivered by Hobson Bullman, General Manager of ARM’s Technology Services Group, and Jugen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors. Bob Smith, Executive Director of the ESD Alliance, gave the keynote at the gala dinner. “It’s fantastic to see this event continuing to do so well, meeting a clear need for a European forum that provides practical, detailed information on state-of-the-art development methodologies,” noted Oliver Bell, DVCon Europe General Chair. “This year’s conference was particularly exciting with three dynamic keynote speeches, overwhelming tutorial and paper submissions, and a vibrant exhibition. Now that DVCon Europe is established as the must-attend event in Europefor engineers to upgrade their skills, we are looking forward to an even larger event in 2017.”

DVCon China

During 2017 DVCon will premier as a one-day event in Shanghai on April 17, 2017. The steering committee is in the process of analyzing a number of excellent paper abstract submissions for its inaugural program.. “Ideas, networking, technical discussions, learning opportunities and exciting exhibits of new products and services. This is what DVCon China will offer to attendees,” stated Andy Liu Hongliang, DVCon China General Chair. “Many hot areas of ASIC design and verification such as UVM, Low Power, IP Reuse, Formal, Mixed-Signal, System Design and Debug Strategies will be distributed throughout the whole conference with lectures, discussions, presentations and demos.”

DVCon U.S. 2016 Is Around the Corner

Thursday, February 18th, 2016

Gabe Moretti, Senior Editor

Within the EDA industry, the Design & Verification Conference and Exhibition (DVCon) has created one of the most successful communities of the 21st century.  Started as a conference dealing with two design languages, Verilog and VHDL, DVCon has grown to cover all aspects of design and verification.  Beginning as a conference based in Silicon Valley, the conference is now held on three continents: America, Asia and Europe.  Both DVCon Europe and DVCon India have shown significant growth, and plans are well on their way to offer a DVCon in China as well.  As Yatin Trivedi, General Chair of this year’s DVCon U.S., says, “DVCon continues to be the premier conference for design and verification engineers of all experience levels. Compared to larger and more general conferences, DVCon affords attendees a concentrated menu of technical sessions – tutorials, papers, poster sessions and panels – focused on design and verification hot topics. In addition to participation in high quality technical sessions, DVCon attendees have the opportunity to take part in the many informal, but often intense, technical discussions that pop up around the conference venue among more than 800 design and verification engineers and engineering managers. This networking opportunity among peers is possibly the greatest benefit to DVCon attendees.”

Professionals attend DVCon to learn and to share, not just to show off their research achievements as a community.  The conference is focused on providing its attendees with the opportunity to learn by offering two days of tutorials as well as frequent networking opportunities.  The technical program offers engineers examples of how today’s problems have been solved under demanding development schedules and budgets.  Ambar Sarkar, Program Chair, offers this advice on the DVCon U.S. 2016 web site: “Find what your peers are working on and interact with the thought leaders in our industry. Learn where the trends are and become a thought leader yourself.”

Grown from the need to verify digital designs, verification technology now faces the need to verify heterogeneous systems that include analog, software, MEMS, and communication hardware and protocols.  Adapting to these new requirements is a task that the industry has not yet solved.

At the same time, methods and tools for mixed-signal or system-level design still need maturing.  The concept of system-level design is being revolutionized as architectures like those required for IoT applications demand heterogeneous systems.

Attendees to DVCon U.S. will find ample opportunity to consider, debate, and compare both requirements and solutions that impact near term projects.

Tutorials and Papers

As part of its mission to provide a learning venue for designers and verification engineers, DVCon U.S. offers two full days of tutorials.  The presentations of the 12 tutorial sessions are divided between Monday and Thursday, separate from the rest of the technical program so they do not conflict and force attendees to make difficult attendance choices.

Accellera has a unique approach to putting together its technical program.  I am slightly paraphrasing this year’s Program Chair, Ambar Sarkar, by stating that DVCon U.S. lets the industry set the agenda, not the conference asking for papers on selected topics.  He told me that the basic question is: “Can a practicing engineer get new ideas and try to use them in his or her upcoming project?” For this reason, the call for papers asks only for abstracts and those that do not meet the request are eliminated.  After a further selection, the authors of the chosen abstracts are asked to submit a full paper.  Those papers are then grouped according to their common subject areas into sessions.  The sessions that emerge automatically reflect the latest trends in the industry.

The paper presentations during Tuesday and Wednesday take the majority of the conference’s time and form the technical backbone of the event.

Of the 127 papers submitted, 36 were chosen to be presented in full.  There will be 13 sessions covering the following areas: UVM, Design and Modeling, Low Power, SystemVerilog, Fault Analysis, Emulation, Mixed-Signal, Resource Management, and Formal Techniques.  Each session offers from 3 to 4 individual papers.

Posters

Poster presentations are selected in the same manner as papers.  A poster presentation is less formal but has the advantage of giving the author the opportunity to interact with a small audience and thus the learning process can be bilateral.  There have been occasions in the past when an abstract submitted as a poster is switched to an oral presentation with the consent of the author.  Such operation is possible because the submitting and selecting process is similar and thus the poster has already been judged as presenting an approach that will be useful to the attendees.

Keynote

This year’s keynote will be delivered by Wally Rhines, the 2015 recipient of the Phil Kaufman Award.  Wally is well known in the EDA industry for both his insight and his track record as the Chairman and CEO of Mentor Graphics.  The title of his address is Design Verification Challenges: Past, Present, and Future.  Dr. Rhines will review the history of each major phase of verification evolution and then concentrate on the challenges of newly emerging problems. While functional verification still dominates the effort, new requirements for security and safety are becoming more important and will ultimately involve challenges that could be more difficult than those we have faced in the past.

Panels: One Good and One Suspect

There are two panels on the conference schedule.  One panel: “Emulation + Static Verification Will Replace Simulation”, scheduled for Wednesday March 2nd at 1:30 in the afternoon looks at the near future verification methods.  Both emulation and static verification use has been increasing significantly.  May be the verification paradigm of the future is to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. Where does that leave RTL simulation? Between a rock and a hard place! Gate-level simulation is already marginalized to doing basic sanity checks. May be RTL simulation will follow. Or will it?

The other panel scheduled for 8:30 in the morning of the same day concerns me a lot.  The title is “Redefining ESL” and the description of the panel is taken from a blog that Brian Bailey, the panel moderator, published on September 24 of 2015.  You can read the blog here: http://semiengineering.com/what-esl-is-really-about/.

In the blog Brian holds the point of view that ESL is not a design flow, it is a verification flow, and it will not take off until the industry recognizes that. Only now are we beginning to define what ESL verification means, but is it too little, too late?  There are a few problems with the panels committee accepting this panel.  To begin with ESL is an outdated concept.  Today’s systems include much more than digital design.  Modern SoCs, even small ones like those fund in IoT applications, include analog, firmware, and MEMS blocks.  All of these are outside of the ESL definition and fall within the System Level Design (SLD) market.

The statement made by Brian that ESL would not be made viable by the introduction of viable High Level Synthesis (HLS) tools is simply false.  ESL verification became a valuable tool only when designers began to use HLS products to automatically derive RTL models from ESL descriptions in SystemVerilog or C/C++ even if HLS covered mostly algorithms expressed in something else besides Verilog, VHDL, or SystemC.

DVCon is the Primary Design and Verification Conference

Friday, February 20th, 2015

Gabe Moretti, Senior editor

DVCon United States opens on March 2nd and ends on March 5th.  If you have not yet made plans to attend and have something to do with developing ICs you should plan to attend.  The growth of this conference has been remarkable.

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera.  That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years.  Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.

The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages.  This year’s conference is the 27th and offers an expanded technical program.  In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year.  Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

The merger of OVI and VI produced significant changes, both for DVCon and for Accellera.  In 2001 DVCon boosted a more efficient organization, both for its technical program and for exhibits.  The source of papers offered for acceptance increased in scope as professionals outside of the Verilog and VHDL users communities became interested in presenting papers at the conference.

As Accellera grew and widened the scope of technical subject it handled, so DVCon increased the technical segments it covered.  First SystemC and shortly thereafter SystemVerilog provided interesting papers and Tutorials.  The verification aspect of the conference was enlivened with focus on UVM (Universal Verification Methodology), TLM (Transaction Level Modeling), testbench construction, and various approaches to testing, including formal techniques.

As the percentage of analog circuits increased in SoC, mixed languages and mixed signal design and verification also became a topic, both in papers and in Tutorials.  In fact one can quickly make a list of the most relevant issues current among electronics engineers by quickly reading the current conference program.

Yatin Trivedi, DVCon General Chair succinctly described the aim of DVCon..  ” DVCon continues to focus on serving the Design and Verification community. DVCon is a conference sponsored by Accellera, in order to promote the adoption of its standards and standards-based methodologies. From the days of exclusive focus on Verilog and VHDL, we have come a long way in including SystemVerilog, SystemC, UPF and UVM. As semiconductor IP became significant to our community of designers and verification engineers, the program has expanded its range of topics. However, our focus remains on design and verification.”

DVCon Europe Is The Wrong Venue

Wednesday, March 19th, 2014

DVCon USA, or should I call it DVCon SV for Silicon Valley, has just concluded another successful year.  The conference has grown significantly, and it compares favorably with other SV based conferences in our industry.  It is now a must attend event for all professionals involved in design verification.  On the heels of such growth Accellera Systems Initiative has announced the first European DVCon conference to be held this October 14 – 15 in Munich Germany.  I believe this is a suboptimal choice.

<b>Toward The Past, Not The Future</b>

Discussions among highly placed members of the Accellera board about starting a conference outside of the US have been going on for at least a couple of years, but the location most talked about was India, not Europe.

In spite of the attraction of Munich in October as a tourist destination, I have reservations as to the wisdom of the choice.  Europe already has a number of EDA and electronics conferences, and one more is not going to make much difference.   Europe is a mature market for the three key corporate powers within Accellera: Mentor, Synopsys, and Cadence. It is not clear what they expect to gain from the conference.

Accellera Technical Working Groups already enjoy good participation from European technologists.  What is needed is to involve representatives from the growth markets.  We need to know what they need, we already know what the US and European users need or think they need.

It would make much more sense to continue to pursue the India idea, although a modification of the venue to China instead of India would make sense.  I agree that the Europe location is easier to arrange.  There are European corporate members in Accellera who can offer support and organizational knowhow, but where is the drive to expand, both technically and economically?

I anticipate rebuttals from some of the board members pointing out that they have a working relationship with the ASP-DAC conference in Japan and thus Asia is serviced, albeit indirectly..  But Japan suffers from the same characteristics as Europe.  Japanese technologists already work within the Accellera Technical Working Groups, and Japan is a mature market for EDA companies.

Growth needs new opportunities and new ideas, not recognition of past and present contributions, no matter how substantial and noteworthy they might have been.  So Accellera board members enjoy your liter of new beer this fall, but think about how many new corporate and technical WG members you could get from locating a conference in China.