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EDA in the year 2017 – Part 1

Thursday, January 12th, 2017

Gabe Moretti, Senior Editor

The EDA industry performance is dependent on two other major economies: one technological and one financial.  EDA provides the tools and methods that leverage the growth of the semiconductor industry and begins to receive its financial rewards generally a couple of year after the introduction of the new product on the market.  It takes that long for the product to prove itself on the market and achieve general distribution.

David Fried from Coventor addressed the most important topics that may impact the foundry business in 2017.  He made two points.

“Someone is going to commit to Extreme Ultra-Violet (EUV) for specific layers at 7nm, and prove it.  I expect EUV will be used to combine 3-4 masks currently using 193i in a multi-patterning scheme (“cut” levels or Via levels) for simplicity (reduced processing), but won’t actually leverage a pattern-fidelity advantage for improved chip area density.

The real density benefit won’t come until 5nm, when the entire set of 2D design rules can be adjusted for pervasive deployment of EUV.  This initial deployment of EUV will be a “surgical substitution” for cost improvement at very specific levels, but will be crucial for the future of EUV to prove out additional high-volume manufacturing challenges before broader deployment.  I am expecting this year to be the year that the wishy-washy predictions of who will use EUV at which technology for which levels will finally crystallize with proof.

7nm foundry technology is probably going to look mostly evolutionary relative to 10nm and 14nm. But 5nm is where the novel concepts are going to emerge (nanowires, alternate channel materials, tunnel FETs, stacked devices, etc.) and in order for that to happen, someone is going to prove out a product-like scaling of these devices in a real silicon demonstration (not just single-device research).  The year 2017 is when we’ll need to see something like an SRAM array, with real electrical results, to believe that one of these novel device

concepts can be developed in time for a 5nm production schedule.”

Rob Knoth, Product Marketing Director, Digital and Signoff Group at Cadence offered the following observation.  “This past year, major IDM and pure-play foundries began to slow the rate at which new process nodes are planned to be released. This was one of the main drivers for the restless semiconductor-based advances we’ve seen the past 50 years.

Going forward, fabs and equipment makers will continue to push the boundaries of process technology, and the major semiconductor companies will continue to fill those fabs. While it may be slowing, Moore’s Law is not “dead.” However, there will be increased selection about who jumps to the “next node,” and greater emphasis will be placed on the ability of the design engineer and their tools/flows/methods to innovate and deliver value to the product. The importance for an integrated design flow to make a difference in product power/performance/area (PPA) and schedule/cost will increase.

The role that engineering innovation and semiconductors play in making the world a better place doesn’t get a holiday or have an expiration date.

The semiconductor market, in turn, depends on the general state of the world-wide economy.  This is determined mostly by consumer sentiment: when consumers buy, all industries benefit, from industrial to financial.  It does not take much negative inflection in consumers’ demand to diminish the requirement for electronic based products and thus semiconductors parts.  That in turn will have a negative effect on the EDA industry.

While companies that sell multi-years licenses can smooth the impact, new licenses, both multi-year and yearly are more difficult to sell and result in lower revenue.

The electronic industry will evolve to deal with increased complexity of designs.  Complex chips are the only vehicle that can make advance fabrication nodes profitable.  It makes no sense decreasing features’ dimensions and power requirements at the cost of increased noise and leakage just for technology sake.  As unit costs increase, only additional functionality can justify new projects.  Such designs will require new methodology, new versions of existing tools, and new industry organization to improve the use of the development/fabrication chain.

Michael Wishart, CEO of Efabless believes that in 2017 we will begin to see full-fledged community design, driven by the need for customized silicon to serve emerging smart hardware products. ICs will be created by a community of unaffiliated designers on affordable, re-purposed 180nm nodes and incorporate low cost, including open source, processors and on-demand analog IP. An online marketplace to connect demand with the community will be a must.

Design Methods

I asked Lucio Lanza of Lanza techVentures what factors would become important in 2017 regarding EDA.  As usual his answer was short and to the point.  “Cloud, machine learning, security and IoT will become the prevailing opportunities for design automation in 2017. Design technology must progress quickly to meet the needs of these emerging markets, requiring as much as possible from the design automation industry. Design automation needs to willingly and quickly take up the challenge at maximum speed for success. It’s our responsibility, as it’s always been.”

Bob Smith, Executive Director of the ESD alliance thinks that in 2017, the semiconductor design ecosystem will continue evolving from a chip-centric (integration of transistors) focus to a system-centric (integration of functional blocks) worldview. While SoCs and other complex semiconductor devices remain critical building blocks and Moore’s Law a key driver, the emphasis is shifting to system design via the extensive use of IP. New opportunities for automation will open up with the need to rapidly configure and validate system-level design based on extensive use of IP.  Industry organizations like the Electronic System Design Alliance have a mission to work across the entire design ecosystem as the electronic design market makes the transition to system-level design.

Wally Rhines, Chairman and CEO of Mentor Graphics addressed the required changes in design as follows: “EDA is a changing.  Most of its effort in the last two decades in the EDA industry has focused on the automation of integrated circuit design. Virtually all aspects of IC design are now automated with the use of computers.  But system design is in the infancy of an evolution to virtual design automation. While EDA has now given us the ability to do first pass functional integrated circuit designs, we are far from providing the same capability to system designers.

What’s needed is the design of “systems of systems”.  That capability is coming.  And it is sooner than you might think.  Designers of planes, trains and automobiles hunger for virtual simulation of their designs long before they build the physical prototypes for each sub-system.  In the past, this has been impossible.  Models were inadequate.  Simulation was limited to mechanical or thermal analysis.  The world has changed.  During 2017, we will see the adoption of EDA by companies that have never before considered EDA as part of their methodology.”

Frank Schirrmeister, Senior Product Management Group Director, System and Verification Group at Cadence offered the following observation.  “IoT that spans across application domains will further grow, especially in the industrial domain. Dubbed in Gernany as “Industrie 4.0”, industrial applications are probably the strongest IoT driver. Value shifts will accelerate from pure semiconductor value to systemic value in IoT applications. The edge node sensor itself may not contribute to profits greatly, but the systemic value of combining the edge node with a hub accumulating data and sending it through networks to cloud servers in which machine learning and big data analysis happens allows for cross monetization. The value definitely is in the system. Interesting shifts lie ahead in this area from a connectivity perspective. 5G is supposed to broadly hit is in 2020, with early deployments in 2017. There are already discussions going on regarding how the connectivity within the “trifecta” of IoT/Hub/Server is going to change, with more IoT devices bypassing the aggregation at the hub and directly accessing the network. Look for further growth in the area that Cadence calls System Design Enablement, together with some customer names you would have previously not expected to create chips themselves.

Traditionally ecosystems have been centered on processor architectures. Mobile and Server are key examples, with their respective leading architectures holding the lion share of their respective markets. The IoT is mixing this up a little as more processor architectures can play and offer unique advantages, with configurable and extensible architectures. No clear winner is in sight yet, but 2017 will be a key year in the race between IoT processor architectures. Even OpenSource hardware architectures are look like they will be very relevant judging from the recent momentum which eerily reminds me of the early Linux days. It’s definitely one of the most entertaining spaces to watch in 2017 and for years to come. “


Standards have played a key role in EDA.  Without them designers would be locked to one vendor for all of the required tools, and given the number of necessary tools very few EDA companies would be able to offer all that is required to complete, verify, and transfer to manufacturing a design.  Michiel Ligthart, President and COO at Verific, sees two standards, in particular, playing a key role in 2017.  “Watch for quite a bit of activity on the EDA standards front in 2017. First in line is the UVM standard (IEEE 1800.2), approved by the Working Group in December 2016. The IEEE may ratify it as early as February. Another one to watch is the next installment of SystemVerilog, mainly a “clarifications and corrections” release, that will be voted on in early 2017 with an IEEE release just before the end of the year. In the meantime, we are all looking at Accellera’s Portable Stimulus group to see what it will come up with in 2017.”

In regards to the Portable Stimulus activity Adnan Hamid, CEO of Breker Verification Systems goes into more details.  “While it’s been a long time coming, Portable Stimulus is now an important component of many design verification flows and that will increase significantly in 2017. The ability to specify verification intent and behaviors reusable across target platforms, coupled with the flexibility in choosing vendor solutions, is an appealing prospect to a wide range of engineering groups and the appeal is growing. While much of the momentum is rooted in Accellera’s Portable Stimulus Working Group, verification engineers deserve credit for recognizing its value to their productivity and effectiveness. Count on 2017 to be a big year for both its technological evolution and its standardization as it joins the ranks of SystemVerilog, UVM and others.


Given the amount of contributions received, it would be overwhelming to present all of them in one article.  Therefore the remaining topics will be covered in a follow-on article the following week.

Electronics: Change Is In The Air

Thursday, November 14th, 2013

Gabe Moretti

I have been lucky to be able to take a relative long vacation on the high seas and in Italy to recharge the batteries and celebrate my retirement.  The time was very enjoyable, but the retirement is not lasting.  There is only so much golf one can play, and so much metaphysics one can study.  So I started to look at EDA and semiconductors industries again because this is what I love to do.  And what I found, having stepped back for almost half a year, may surprise a few.

The Problem

The electronics industry is on a verge of a drastic change, and with it EDA and to a lesser extent the semiconductors industry will have to change as well.   Designers have since the middle of the 70′s used a semiconductors industry that has grown according to Moore’s law.  This so called law, which in fact is simply a prediction, is based on the ability of the semiconductors industry to shrink the size of transistors according to a predictable schedule.  So, in practice, every new design only confronted the obstacle of utilizing more transistors in a manner that generated revenue.

Before now there has been only one physical hurdle to overcome: the wavelength of visible light.  The shift to UV light was accomplished by the semiconductors company without any fundamental impact in the methods followed by designers to develop IC’s.  Of course complexity brought drastic changes to the design and development methods.  When circuits became too large to handle in a timely and reliable fashion, EDA provided Hardware Description Languages (HDLs) like Verilog and VHDL.  When Verilog became too hardware oriented to support very large designs, EDA found C and C++ and developed the tools required to translate those descriptions into hardware primitives.  But in general the industry has spent billions developing a large number of engineers that understand logic but are almost ignorant of physics.

Such deficiency of knowledge has impacted the cost of development of ICs below 90 nm, as second order parasitic effects have seriously impacted the behavior of circuits.  Cross talk and leakage, above all, must now be dealt with.  Doing so up front using sound physics and logic design is still rare.  Designers are still fixing errors instead of avoiding them.

Warning bells are being sounded at the 20 nm process level.  Development, design, and manufacture of these devices are more costly and less reliable than expected.  Development costs are in the hundreds of million of dollars, and yields are not as good as expected.  Also electronics companies used to “purchase” manufacturing insurance by relying on a second source for IC fabrication.  This practice has been abandoned, not because of regulations or competiveness among foundries but because a second source is almost equivalent to a second design.

At the 14 nm process node level we are now finding what physicists have found some years ago: things are different at atomic and near atomic sizes.  The industry is approaching the time when quantum events are likely to occur within an IC.  It is fine to read that company X has employed EDA vendor’s Y tools to produce a working test chip at foundry Z.  It means we can survive, it does not mean we can produce and remain in business.  The process node will be real only after we reach a steady 50% or more yield level.

A Proposed Scenario

There are at least two directions available to us to solve the problem, and both are required.

From a business and organization point of view, we need the means to build a coalition of tightly integrated partners that covers the idea, design, realization, manufacturing flow.  Electronics companies, EDA vendors, foundries, and equipment providers must all be integrated into a producing organization and understand well each strengths and weaknesses.  What can each provide and what each must have in order to succeed.

Design of ICs must also change.  It is not enough to consider a block as a portable sub-circuit that can be instantiated reliably anywhere in the topology.  Engineers will have to deal with “neighborhoods.”  The electrical and physical influence of a transistor or a cell on its surrounding environment will change with the environment and with its behavioral profile.  It may be necessary to build to similar circuits placed at different parts of the die and activate them according to what else is happening on the chip at the time.  The age of 97% or so silicon utilization has been left behind for some years.

On board heuristic circuitry may have to be employed in order to enable power and clocking circuitry in various locations of the chip as a function of its present and predicted state.  It may even be necessary to stop and resume operations while fully maintaining the logic state in order to survive a damaging transitory physical event.  A thousandth of a second is a long time in atomic terms.

So while foundries and equipment providers deal with how to arrange atoms into desired structures, designers and EDA tools developers will have to deal with how to design a circuit not as a static thing that will eventually execute some functions, but as a dynamic entity that changes logical and physical properties as it executes those functions while respecting the boundaries imposed by the process to be used.


Are we structured correctly to address the coming challenges?  Are the financial arrangements used presently the correct ones?  If not can they be modified or do we need to start from scratch?  How do we train a new set of designers that intuitively can foresee and prevent or avoid a totally new set of problems not faced by the present generation of design engineers?  It will take a very large investment and significant time to reach the same efficiency at the atomic level that we have achieved today at the UV/nano level.