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Posts Tagged ‘FPGA’

Grant Pierce Named BoD Chair of the ESD Alliance

Tuesday, February 21st, 2017

Gabe Moretti, Senior Editor

The ESD Alliance (ESDA) has elected Grant Pierce (CEO of Sonics) as its Chairman of the Board a few weeks ago.  Grant is only the second Chair that is not a high level executive of one of the three big three EDA companies to hold the title, and the first since the organization, formerly EDAC renamed itself.  During the EDAC days it was customary for the CEOs of Cadence, Mentor and Synopsys to pass the title among themselves in an orderly manner.  The organization then reflected the mission of the EDA industry to support the development of hardware intensive silicon chips following Moore’s Law.

Things have changed since then, and the consortium responded by first appointing a new executive director, Bob Smith, then changing its name and its mission.  I talked with Grant to understand his view from the top.

Grant Pierce, Sonics CEO

Grant pointed out that: “We are trying to better reflect what has happened in the market place, both in terms of how our customers have developed further in the world of system on chip and what we have seen in the development of the EDA world where today the IP offerings in the market, both those from independent companies but also those from EDA companies are critical and integral to all the whole ecosystem for building today’s modern chips.”

Grant pointed out that ESDA has expanded its focus and has embraced not only hardware design and development but also software.  That does not mean, Grant pointed out, that the EDA companies are loosing importance but instead they are gaining a seat at the table with the software and the system design community in order to expand the scope of their businesses.

From my point of view, I interjected, I see the desired change implemented very slowly, still reacting to and not anticipating new demands.  So what do you think can happen in the next twelve months?

“From an ESDA point of view you are going to see us broadening the membership.” answered Grant.  ”We are looking to see how we can expand the focus of the organization through its working groups to zero-in on new topics that are broader than the ones that are currently there.  Like expanding beyond what is a common operating system to support for example.  I think you will see at a minimum two fronts, one opening on the software side while at the same time continuing work on the PPA (Power, Performance, Area) issues of chip design.  This involves a level of participation from parties that have not interacted this organization before.”

Grant believes that there should be more emphasis on the needs of small companies, those where innovation is taking place.  ESDA needs to seek the best opportunity to invigorate those companies.  “At the same time we must try to get system companies involved in an appropriate fashion, at least to the degree that they represent the software that is embedded in a system” concluded Grant.

We briefly speculated on what the RISC 5 movement might mean to ESDA.  Grant does not see much value for ESDA to focus on a specific instruction set, although he conceded that there might be value if RISC 5 joined ESDA.  I agree with the first part of his judgement, but I do not see any benefit to either party, or the industry for that matter, associated with RISC 5 joining ESDA.

From my point of view ESDA has a big hurdle to overcome.  For a few years, before Bob Smith was named executive director, EDAC was somewhat stagnant, and now it must catch up with market reality and fully address the complete system issue.  Not just hardware/software, but analog/digital, and the increased use of FPGA and MEMS.

For sure, representing an IP company gives Grant an opportunity to stress a different point of view within ESDA than the traditional EDA view.  The IP industry would not even exist without a system approach to design and it has changed the way architects think when first sketching a product on the back of an envelope.

Intel Acquisition of Altera: the Worth of Rumors

Monday, April 13th, 2015

Gabe Moretti, Senior Editor

In the last two weeks John Cooley, the owner of the Deep Chip column. has spent a significant amount of words commenting on the Wall Street Journal story regarding the offering by Intel to acquire Altera.  At the end of the two weeks I have learned a full list of short term negative events possible that can result from an acquisition, thanks to John.  I also learned from the usual anonymous contributor that at least two projects using FPGA devices to increase search speed in a data center did not meet expected goals.  This second contribution was in response to the reason the Wall Street article gave for Intel’s interest in Altera.  The writer of the Deep Chip piece, who signs himself or herself “Been There, Done That” states that the main reason for Intel acquisition is the market expansion in FPGA due to the need to use FPGA devices in data centers to increase search speed.

By the way, I really wish John would rely less on these anonymous contributions because more frequently than is comfortable, such pieces end up having ulterior motives.  “Caveat lector” reader beware, is the approach to be taken with these contributions.   The anonymous contribution published this week regarding the supposed technological reason for the acquisition of Altera by Intel is particularly off the mark.

“Been There, Done That” starts from a premise that is hardly defendable.  In my job I talk to both financial analysts and editors.  We all know the names of the few analysts that truly follow our industry: none of them is connected with this particular story.  Generally financial editors have only a superficial knowledge of the industry in general. The Deep Chip contributor took the Wall Street explanation for the acquisition as a real reason for such move.  Wrong, really wrong.  Contrary to the Wall Street editor, Intel has people that do not just rely on a Google search to find out the potential of the acquisition, both from a technological and a financial point of view.  FPGA in the data center is likely to have been a topic found with a Google search, knowing how good Intel is at pointing the financial community in the wrong direction when they want.  I can assure you that the real reason for the acquisition, if the acquisition will indeed take place, may never be known.  Reasons will be given, but the real, fundamental one, may never be known outside a small group at Intel.  Please do not be so naïve to assume that every acquisition offer has the goal to actually end up in an acquisition.  Do you remember how much money Carl Icahn made with is “failed” acquisition of Mentor by Cadence?

The anonymous Deep Chip contributor uses a published paper from Microsoft personnel that stated that their project of using FPGA devices to increase search speed only doubled the speed. “Been There, Done That” states that “my engineers and I” have identified 14 failures in such an approach.  The best I can deduct is that that particular engineering team has also used FPGAs in an attempt to increase the search speed of a system and found that an ASIC solution worked better in their particular case.  I ask myself why an entire engineering team has the time to analyze a Wall Street article instead of doing productive work?  Is it to derail the acquisition or to ridicule Intel or may be the Wall Street Journal?

The stated reasons for the projected failure of the acquisition rests on one Microsoft project and the experience of another engineering team.  I am sure that the writer is extremely familiar with the project he or she led, but probably not intimately familiar with the purpose of the Microsoft project.  Sometimes collateral results are as or more important than the stated purpose of the project.  Let me point out that the Microsoft project was not meant to deliver a sellable product and that it may have been only one of a number of parallel projects.

So “Been There, Done That” fails to prove that the assumed technical reason for the acquisition is misguided, since it is likely that the reason does not exist.  Unless, of course, he or she works for Intel.  In which case good luck hiding under a pseudonym.  I do not presume to know the reason or reasons Intel has to acquire Altera but I can point out that the FPGA market is healthy and likely to grow, that there might be technological synergy between FPGA and IC engineering (in either or both directions), and that it may be more efficient to acquire experienced human resources through an acquisition than in the open market.

FPGA Prototyping Could Become Mainstream Again

Thursday, February 12th, 2015

Gabe Moretti, Senior Editor

Since the very early days of ASIC design engineers have prototyped their ASIC development using FPGA devices in order to debug and verify the design.  The advantage is that the Device Under Test (DUT) runs at speeds that are much greater than those achievable with traditional simulation and in most cases equal or nearly equal those of the actual device.  This is particularly useful in debugging the product’s  firmware, but it also helps in various hardware situations.

FPGA prototyping is not just a thing of the past, before the introduction of emulators, it is a technique used today by many development teams.  Given the imminent development and introduction o a large number of small systems in the IoT architecture, I expect that there will be even more use of FPGA prototyping.  I asked the input of three representatives of EDA companies to get a better picture of the state of affairs.  One, Zibi Zalewski, General Manger of the Hardware Products Division at Aldec, represents the views of what I consider a middle size vendor, while Troy Scott, Product Marketing Manager at Synopsys represent the view of a large company that has a group dedicated explicitly to supporting FPGA prototyping of ASIC designs.  Frank Schirrmeister, Group Director for Product Marketing of the System Development Suite at Cadence,represents a company that competes for the number one position in the emulation and acceleration tools market.

Due to the length of the resulting article I chose to publish the three contributions as separate articles, and to group them herein my blog to give you, the reader, additional flexibility in covering the topic.

A Historical Approach

Zibi reviewed FPGA prototyping from an historical point of view.  He reminisced about his days as a development engineer and compared the requirement at that time with the development environment available today.  You can read his contribution at: http://chipdesignmag.com/sld/blog/2015/02/12/asic-prototyping-with-fpga/.

Using FPGA Prototyping for Faster System Validation

Synopsys has always been focused on the design and development of semiconductor devices since its inception, and has entered the market of FPGA based designs mostly in order to support ASIC prototyping.  You can read what Troy Scott sent me at this address: http://chipdesignmag.com/sld/blog/2015/02/12/asic-prototypes-take-the-express-lane-for-faster-system-validation/.

A Prototyping with FPGA Approach

Frank Schirrmeister provided a view of prototyping that frames it within the present efforts to decrease development time, the so called “shift left” approach or the recently proposed Agile IC Methodology.  You can read his thoughts here: http://chipdesignmag.com/sld/blog/2015/02/12/a-prototyping-with-fpga-approach/.

Conclusion

Although some may think that FPGA prototyping is a methodology that has seen its prime, the focus on IoT architecture, which use a large number of small, focused, systems, will revive this development method, since, in many cases, companies will be able to avail themselves of a fixed general purpose control subsystem and a function based data acquisition subsystem.  I in fact, envision development systems available fr purchase that offer a control and data analysis standard system and allow designers to include the sensor and circuitry specific to the function to generate a complete FPGA based prototyping environment.