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Posts Tagged ‘Mentor’

Grant Pierce Named BoD Chair of the ESD Alliance

Tuesday, February 21st, 2017

Gabe Moretti, Senior Editor

The ESD Alliance (ESDA) has elected Grant Pierce (CEO of Sonics) as its Chairman of the Board a few weeks ago.  Grant is only the second Chair that is not a high level executive of one of the three big three EDA companies to hold the title, and the first since the organization, formerly EDAC renamed itself.  During the EDAC days it was customary for the CEOs of Cadence, Mentor and Synopsys to pass the title among themselves in an orderly manner.  The organization then reflected the mission of the EDA industry to support the development of hardware intensive silicon chips following Moore’s Law.

Things have changed since then, and the consortium responded by first appointing a new executive director, Bob Smith, then changing its name and its mission.  I talked with Grant to understand his view from the top.

Grant Pierce, Sonics CEO

Grant pointed out that: “We are trying to better reflect what has happened in the market place, both in terms of how our customers have developed further in the world of system on chip and what we have seen in the development of the EDA world where today the IP offerings in the market, both those from independent companies but also those from EDA companies are critical and integral to all the whole ecosystem for building today’s modern chips.”

Grant pointed out that ESDA has expanded its focus and has embraced not only hardware design and development but also software.  That does not mean, Grant pointed out, that the EDA companies are loosing importance but instead they are gaining a seat at the table with the software and the system design community in order to expand the scope of their businesses.

From my point of view, I interjected, I see the desired change implemented very slowly, still reacting to and not anticipating new demands.  So what do you think can happen in the next twelve months?

“From an ESDA point of view you are going to see us broadening the membership.” answered Grant.  ”We are looking to see how we can expand the focus of the organization through its working groups to zero-in on new topics that are broader than the ones that are currently there.  Like expanding beyond what is a common operating system to support for example.  I think you will see at a minimum two fronts, one opening on the software side while at the same time continuing work on the PPA (Power, Performance, Area) issues of chip design.  This involves a level of participation from parties that have not interacted this organization before.”

Grant believes that there should be more emphasis on the needs of small companies, those where innovation is taking place.  ESDA needs to seek the best opportunity to invigorate those companies.  “At the same time we must try to get system companies involved in an appropriate fashion, at least to the degree that they represent the software that is embedded in a system” concluded Grant.

We briefly speculated on what the RISC 5 movement might mean to ESDA.  Grant does not see much value for ESDA to focus on a specific instruction set, although he conceded that there might be value if RISC 5 joined ESDA.  I agree with the first part of his judgement, but I do not see any benefit to either party, or the industry for that matter, associated with RISC 5 joining ESDA.

From my point of view ESDA has a big hurdle to overcome.  For a few years, before Bob Smith was named executive director, EDAC was somewhat stagnant, and now it must catch up with market reality and fully address the complete system issue.  Not just hardware/software, but analog/digital, and the increased use of FPGA and MEMS.

For sure, representing an IP company gives Grant an opportunity to stress a different point of view within ESDA than the traditional EDA view.  The IP industry would not even exist without a system approach to design and it has changed the way architects think when first sketching a product on the back of an envelope.

EDA in the year 2017 – Part 1

Thursday, January 12th, 2017

Gabe Moretti, Senior Editor

The EDA industry performance is dependent on two other major economies: one technological and one financial.  EDA provides the tools and methods that leverage the growth of the semiconductor industry and begins to receive its financial rewards generally a couple of year after the introduction of the new product on the market.  It takes that long for the product to prove itself on the market and achieve general distribution.

David Fried from Coventor addressed the most important topics that may impact the foundry business in 2017.  He made two points.

“Someone is going to commit to Extreme Ultra-Violet (EUV) for specific layers at 7nm, and prove it.  I expect EUV will be used to combine 3-4 masks currently using 193i in a multi-patterning scheme (“cut” levels or Via levels) for simplicity (reduced processing), but won’t actually leverage a pattern-fidelity advantage for improved chip area density.

The real density benefit won’t come until 5nm, when the entire set of 2D design rules can be adjusted for pervasive deployment of EUV.  This initial deployment of EUV will be a “surgical substitution” for cost improvement at very specific levels, but will be crucial for the future of EUV to prove out additional high-volume manufacturing challenges before broader deployment.  I am expecting this year to be the year that the wishy-washy predictions of who will use EUV at which technology for which levels will finally crystallize with proof.

7nm foundry technology is probably going to look mostly evolutionary relative to 10nm and 14nm. But 5nm is where the novel concepts are going to emerge (nanowires, alternate channel materials, tunnel FETs, stacked devices, etc.) and in order for that to happen, someone is going to prove out a product-like scaling of these devices in a real silicon demonstration (not just single-device research).  The year 2017 is when we’ll need to see something like an SRAM array, with real electrical results, to believe that one of these novel device

concepts can be developed in time for a 5nm production schedule.”

Rob Knoth, Product Marketing Director, Digital and Signoff Group at Cadence offered the following observation.  “This past year, major IDM and pure-play foundries began to slow the rate at which new process nodes are planned to be released. This was one of the main drivers for the restless semiconductor-based advances we’ve seen the past 50 years.

Going forward, fabs and equipment makers will continue to push the boundaries of process technology, and the major semiconductor companies will continue to fill those fabs. While it may be slowing, Moore’s Law is not “dead.” However, there will be increased selection about who jumps to the “next node,” and greater emphasis will be placed on the ability of the design engineer and their tools/flows/methods to innovate and deliver value to the product. The importance for an integrated design flow to make a difference in product power/performance/area (PPA) and schedule/cost will increase.

The role that engineering innovation and semiconductors play in making the world a better place doesn’t get a holiday or have an expiration date.

The semiconductor market, in turn, depends on the general state of the world-wide economy.  This is determined mostly by consumer sentiment: when consumers buy, all industries benefit, from industrial to financial.  It does not take much negative inflection in consumers’ demand to diminish the requirement for electronic based products and thus semiconductors parts.  That in turn will have a negative effect on the EDA industry.

While companies that sell multi-years licenses can smooth the impact, new licenses, both multi-year and yearly are more difficult to sell and result in lower revenue.

The electronic industry will evolve to deal with increased complexity of designs.  Complex chips are the only vehicle that can make advance fabrication nodes profitable.  It makes no sense decreasing features’ dimensions and power requirements at the cost of increased noise and leakage just for technology sake.  As unit costs increase, only additional functionality can justify new projects.  Such designs will require new methodology, new versions of existing tools, and new industry organization to improve the use of the development/fabrication chain.

Michael Wishart, CEO of Efabless believes that in 2017 we will begin to see full-fledged community design, driven by the need for customized silicon to serve emerging smart hardware products. ICs will be created by a community of unaffiliated designers on affordable, re-purposed 180nm nodes and incorporate low cost, including open source, processors and on-demand analog IP. An online marketplace to connect demand with the community will be a must.

Design Methods

I asked Lucio Lanza of Lanza techVentures what factors would become important in 2017 regarding EDA.  As usual his answer was short and to the point.  “Cloud, machine learning, security and IoT will become the prevailing opportunities for design automation in 2017. Design technology must progress quickly to meet the needs of these emerging markets, requiring as much as possible from the design automation industry. Design automation needs to willingly and quickly take up the challenge at maximum speed for success. It’s our responsibility, as it’s always been.”

Bob Smith, Executive Director of the ESD alliance thinks that in 2017, the semiconductor design ecosystem will continue evolving from a chip-centric (integration of transistors) focus to a system-centric (integration of functional blocks) worldview. While SoCs and other complex semiconductor devices remain critical building blocks and Moore’s Law a key driver, the emphasis is shifting to system design via the extensive use of IP. New opportunities for automation will open up with the need to rapidly configure and validate system-level design based on extensive use of IP.  Industry organizations like the Electronic System Design Alliance have a mission to work across the entire design ecosystem as the electronic design market makes the transition to system-level design.

Wally Rhines, Chairman and CEO of Mentor Graphics addressed the required changes in design as follows: “EDA is a changing.  Most of its effort in the last two decades in the EDA industry has focused on the automation of integrated circuit design. Virtually all aspects of IC design are now automated with the use of computers.  But system design is in the infancy of an evolution to virtual design automation. While EDA has now given us the ability to do first pass functional integrated circuit designs, we are far from providing the same capability to system designers.

What’s needed is the design of “systems of systems”.  That capability is coming.  And it is sooner than you might think.  Designers of planes, trains and automobiles hunger for virtual simulation of their designs long before they build the physical prototypes for each sub-system.  In the past, this has been impossible.  Models were inadequate.  Simulation was limited to mechanical or thermal analysis.  The world has changed.  During 2017, we will see the adoption of EDA by companies that have never before considered EDA as part of their methodology.”

Frank Schirrmeister, Senior Product Management Group Director, System and Verification Group at Cadence offered the following observation.  “IoT that spans across application domains will further grow, especially in the industrial domain. Dubbed in Gernany as “Industrie 4.0”, industrial applications are probably the strongest IoT driver. Value shifts will accelerate from pure semiconductor value to systemic value in IoT applications. The edge node sensor itself may not contribute to profits greatly, but the systemic value of combining the edge node with a hub accumulating data and sending it through networks to cloud servers in which machine learning and big data analysis happens allows for cross monetization. The value definitely is in the system. Interesting shifts lie ahead in this area from a connectivity perspective. 5G is supposed to broadly hit is in 2020, with early deployments in 2017. There are already discussions going on regarding how the connectivity within the “trifecta” of IoT/Hub/Server is going to change, with more IoT devices bypassing the aggregation at the hub and directly accessing the network. Look for further growth in the area that Cadence calls System Design Enablement, together with some customer names you would have previously not expected to create chips themselves.

Traditionally ecosystems have been centered on processor architectures. Mobile and Server are key examples, with their respective leading architectures holding the lion share of their respective markets. The IoT is mixing this up a little as more processor architectures can play and offer unique advantages, with configurable and extensible architectures. No clear winner is in sight yet, but 2017 will be a key year in the race between IoT processor architectures. Even OpenSource hardware architectures are look like they will be very relevant judging from the recent momentum which eerily reminds me of the early Linux days. It’s definitely one of the most entertaining spaces to watch in 2017 and for years to come. “

Standards

Standards have played a key role in EDA.  Without them designers would be locked to one vendor for all of the required tools, and given the number of necessary tools very few EDA companies would be able to offer all that is required to complete, verify, and transfer to manufacturing a design.  Michiel Ligthart, President and COO at Verific, sees two standards, in particular, playing a key role in 2017.  “Watch for quite a bit of activity on the EDA standards front in 2017. First in line is the UVM standard (IEEE 1800.2), approved by the Working Group in December 2016. The IEEE may ratify it as early as February. Another one to watch is the next installment of SystemVerilog, mainly a “clarifications and corrections” release, that will be voted on in early 2017 with an IEEE release just before the end of the year. In the meantime, we are all looking at Accellera’s Portable Stimulus group to see what it will come up with in 2017.”

In regards to the Portable Stimulus activity Adnan Hamid, CEO of Breker Verification Systems goes into more details.  “While it’s been a long time coming, Portable Stimulus is now an important component of many design verification flows and that will increase significantly in 2017. The ability to specify verification intent and behaviors reusable across target platforms, coupled with the flexibility in choosing vendor solutions, is an appealing prospect to a wide range of engineering groups and the appeal is growing. While much of the momentum is rooted in Accellera’s Portable Stimulus Working Group, verification engineers deserve credit for recognizing its value to their productivity and effectiveness. Count on 2017 to be a big year for both its technological evolution and its standardization as it joins the ranks of SystemVerilog, UVM and others.

Conclusion

Given the amount of contributions received, it would be overwhelming to present all of them in one article.  Therefore the remaining topics will be covered in a follow-on article the following week.

EDA has not been successful at keeping its leaders

Wednesday, January 4th, 2017

Gabe Moretti, Senior Editor

I have often wondered why when a larger EDA company acquires a smaller one, the acquired CEO ends up, in a relatively short time, leaving and either joining a new start-up or a venture capital firm.  It seemed to me that that CEO thought enough of the buyer to predict his (or hers) employees and product(s) would prosper in the new environment when accepting to be acquired.  So, why leave?  It could just not be a matter of strong contrasting personalities.  I think I found the answer over the Christmas break.

I read the book “Skunk Works” by Ben R. Rich.  The book is a factual history of development projects that were carried out while Ben was first there as an employee and eventually its leader.  During his years at the Skunk Works Mr. Rich was part of the exceptional successes of the U-2 and SR-71 spy planes, and of the F117A stealth bomber.  All those projects were run independently of corporate overseers, used a comparatively small dedicated team, and modified the project when necessary to achieve the established goal.

Two major points made in the book apply both to the EDA industry and to industry in general.  First “Leaders are natural born: managers must be trained” and second “There is no substitute for astute managerial skill on any project”.

Many start-up CEOs are born leaders and do not fit well within an organization where projects are managed in a bureaucratic manner using a rigid reporting structure.  An ex-CEO will soon find such work environment counter-productive.  Successful projects need to react quickly to changing realities and parameters.  Often in the life of a project the team discovers new opportunities or new obstacles that come to light because of the work being done.  The time spent explaining and justifying the new alternative will impact the success of the project, especially if the value of the presented alternative is not fully understood by top executives or the new managers do not understand the new corporate politics.

I think that the best use of an acquired CEO is to allow him or her to continue to be an entrepreneur within the acquiring company.  This does not mean to use his talent to continue to lead the just acquired team. He can look for new opportunities within his area of expertise and possibly build a new team that will produce a new product.  In this way the acquiring company increases its ROI form the acquisition, even at the cost of increased compensation to both the CEO and his new team at the successful completion of their work.

In general Synopsys has managed to retain acquired CEOs, while Cadence has not.

The behavior in the EDA industry, with very few well known exceptions, has been to seek a quick reward through an acquisition that will satisfy financially both the venture capitalists and the original start-up team.  Once the acquisition price is monetized, many people leave the industry seeking to capitalize on their financial gains in other ways.  Thus the EDA industry must grow through the entrance of new people with new ideas but little if any experience in the industry.  The result is many academic brilliant ideas that result in failed start-ups.  Individuals with brilliant ideas are not usually good leaders or managers, and good managers do not generally possess the creativity to conceive a breakthrough product.

In its history the EDA industry has paid the price of creating both leaders and excellent managers, but has yet to find a way to retain them.  Of course there are a few exceptions, nothing is ever black and white, but the exceptions are few.  It will be interesting to see, after a couple of years, how Siemens will have handled the Mentor Graphics acquisition.  Will Mentor’s creativity improve?  Will the successful team remain?  Will they use the additional resource in an entrepreneurial manner, or either leave or adjust to a more relaxed big company life?

Siemens Acquisition of Mentor Graphics is Good for EDA

Tuesday, November 15th, 2016

Gabe Moretti, Senior Editor

Although Mentor has been the subject of take-over attempts in the past, the business specifics of the transactions have never been favorable to Mentor.  The acquisition by Siemens, instead, is a favorable occurrence for the third largest EDA company.  This time both companies obtain positive results from the affair.

Siemens acquires Mentor following the direction set forth in 2014 when its Vision 2020 was first discussed in public.  The 6 year plan describes steps the company should take to better position itself for the kind of world it envisions in 2020.

The Vision 2020 document calls for operational consolidation and optimization during the years 2016 and 2017.  It also selects three of its business division as critical to corporate growth.  It calls it the E-A-D system that include: Digitalization, Automation, and Electrification.

Although it is possible that Mentor technology and products may be strategic in Electrification, they are of significant importance in the other two areas: Digitalization and Automation.  Digitalization, for example, includes vehicle automation, including smart cars and vehicle to vehicle communication.  Mentor already has an important presence in the automotive industry and can help Siemens in the transition to state of the art car management by electronic systems to the innovation of new systems required by the self-driving automobile and the complete integration of the components into an intelligent systems including vehicle-to-vehicle communication.

Mentor also has experience in industrial robots and what is, in my mind, more remarkable, is that the PCB and cabling portions of Mentor, often minimized in an EDA industry dominated by the obsession of building ICs, are the parts that implement and integrate the systems in the products designed and built by third parties.

With its presence in the PCB and cabling markets, Mentor can bring additional customers to Siemens as well as insight in future marketing requirements and limitations that will serve extremely well in designing the next generation industrial robots.

Of course, Mentor will also find an increased internal market as other divisions of Siemens not part of the E-A-D triumvirate will utilize its products and services.

Siemens describes itself as an employee oriented company, so present Mentor employee should not have to fear aggressive cost cutting and consolidation.  Will Mentor change? Of course, it will adapt gradually to the new requirements and opportunities the Siemens environment will create and demand, but the key word is “gradually”.  Contrary to the acquisition of ARM by SoftBank, where the acquiring company had no previous activity in ARM’s business, Siemens has been active in EDA internally, both in its Research Lab and strong connections with university programs that originated a number of European EDA startups.  Siemens executives have an understanding of what EDA is all about and what it takes to be successful in EDA.  The result, I expect, is little interference and second guessing which translates in continuous success for Mentor for as long as they are capable of it.

Wil other EDA companies benefit from this acquisition? I tink they will.  First of all it attracts more attention to our industry by the financial community, but it also is likely to increase competition among the “big 3” forcing Cadence and Synopsys to focus more on key markets and while diversifying into related markets like optical, security, software development for example.  In addition I do not see the reason for an EDA company to enter into a business partnership with some of its customers to explore new revenue generating business models.

DAC Official Results Are In

Thursday, June 23rd, 2016

Gabe Moretti, Senior Editor

Have already covered DAC in a previous blog, but a couple of days ago I received an email from Michelle Clancy, 53rd DAC PR/Marketing Chair, reporting on the conference attendance.  I have additional observations on the Austin conference as a result of the release.

As far as I am concerned the structure of the release was poor.  Readers were guided to consider the overall attendance numbers which was quite small. The increment in overall badges between the 2013 Austin DAC and this year is an increase of 125 badges.  That is an increase of 2.1% significantly less that the increase in the revenue of the EDA industry in the same span of time.  And in addition we have witnessed the growth of related industries who have a presence in and around Austin such as embedded systems and IoT.

What should be underlined is the difference between conference attendees badges from 2013 and 2016.  There were 719 more conference badge this year, while the free “I LOVE DAC” passes were down 564 for the same comparison.  To me this are the important data.  It means that there were fewer “tire kickers” who collect souvenirs and more technical program or tutorial attendees than in 2013.  These are the numbers that indicate success, but the press release did not dwell on them.

I also find it telling that the quote in the release from Howard Pakosh, managing partner of TEKSTART, which provides interim sales, marketing and business development capital to high-tech entrepreneurs, observes “The people we’ve been talking to in Austin are actually looking for information and solutions; they’re not just here because it’s an easy commute from Silicon Valley.”  Obviously Mr. Pakosh finds it a waste of time to exhibit in San Francisco.

My experience on the exhibit floor was different.  The fact that Synopsys chose to send fewer PR and marketing persons to Austin was a negative point for me.  It was difficult to find the right person to discuss business with.  The company also did not have their usual press/analysts dinner and this is unfortunate since their new message “silicon to software” was not well presented on the floor.  I left the conference without understanding the message, especially since I was told in my meeting with corporate marketing that their effort was to promote products from Coventry and Codenomicon to markets outside the electronics business.  Are those products the “software” they are talking about?  What about embedded software for all sort of applications, including those who use their ARC processors?

Cadence and Mentor booths were better staffed, at least I met all the professionals I needed to meet. It is of course time that Cadence realizes that “The Denali Party” does not take the place of a serious dinner with press and analysts.  The Heart of Technology party is a better choice if one wants music and drinks and it supports a good cause.  I go to DAC to do business, not to drink cheap drinks and fight for food in a crowded buffet line.

It is of course expected that the technical program offered by DAC covers leading edge issues and opportunities.  This part of DAC was well organized and run.

If the DAC committee sees the need to defend the choice of Austin as the venue for the conference, then why use the venue next year?  Clearly the have determined that Austin is a viable location.  I for one, did enjoy Austin as a host city and found the convention hall pleasant and well equipped.  Of course the distance between both sessions and exhibits to the press room was not at all convenient, but I do understand that the press room location was chosen because it allowed the building of the necessary temporary meeting rooms.

Cadence’s Allegro and Orcad Updates

Tuesday, May 31st, 2016

Gabe Moretti, Senior Editor

At the beginning of May, in time for CDNLive, Cadence announced major upgrades for its Allegro and Orcad products.  The Printed Circuit Board (PCB) sector of our industry gets the second cousin treatment in an industry so focused on silicon products.  Yet PCB play a very important role in system design, one that is almost never recognized by the ESL tools.  I cannot name an ESL tool that allows architects to evaluate the topology of a system on a PCB.  PCB designers are always left with the task of accommodating the electronic system within the mechanical confines of the product.  Naturally this brings about thermal and electrical issues that are not at all considered by the IC designers.

The new versions introduced by Cadence do not attempt to address this problem either, although they have improved the interoperability between Allegro and Sigrity to shorten PCB design and verification time.  Other new capabilities in the Allegro product include:

Rigid-Flex design enhancements, inter-layer checks for both flex and rigid flex, a new native 3D engine, and finally a Programmable Interface with the Sigrity tool.

By looking at the capabilities offered by similar products from Mentor and Zuken, it turns out that Allegro does not offer any capability that is not already present in Mentor ‘s Xploration or Zuken’s CR8000 products.  All three products address the problem of PCB design and verification in different manner, so that a choice among them is a matter of methods more than of capability.

What is interesting within the PCB market is that all three leading vendors have chosen a dual approach.  Cadence with Allegro and OrCAD, Mentor with Xpedition and PADS, and Zuken with the CR family and CADSTAR.  There seems to be a real division among PCB designers that supports such strategy.  OrCAD, PADS, and CADSTAR aim to support the individual designer who works on a less challenging PCB design and whose verification requirements are less demanding.  Allegro, Xpedition, and CR8000 (or CR7000 for that matter) support team design and a verification cycle that deals with power distribution, IR- Drop, noise, and thermal issues among others.

While both Mentor and Zuken address the PCB market by addressing PCB design and verification problems in their own importance, Cadence serves this market as a function of what an IC designer needs from the PCB.  The lack of consideration by Cadence for the role that a PCB plays is system design is therefore more intriguing.  It would seem to me that Cadence would be the one concerned with co-design and co-verification of IC and PCB, but this is not the case at all.  In all three cases the IC, or ICs are taken as given, there is no possibility to tradeoff IC characteristics and a PCB characteristics.  True enough, in most cases the IC is what it is, it comes from a third party, and thus the PCB designer must adapt to a set of characteristics that are unchangeable.  But that is not always the case.  Some ICs come as a family with different electrical specification, and evaluating various flavors of a CPU or MCU should be an easy thing to do.

Unfortunately, PCB designers are mostly ignored by DAC.  Zuken is not even on the exhibitors list this year, so attendees will not get the opportunity to compare products, beside may be Mentor’s and Cadence’s.  I  wrote “may be” because both booths will certainly underscore IC design and there will be a high level of discourse about IoT.  But you need to ask, if you want to find someone on the booth that can demo a PCB product.

A Point to Ponder from Gary Smith’s DAC Presentation

Monday, July 27th, 2015

Gabe Moretti, Senior Editor

The integration of electrical and mechanical tools is one of the subjects that Gary Smith covered in his presentation at this year’s DAC.  It is clear that we are finally reaching an understanding among EDA analysts that a system is more than just its electronic and electrical portions.  Gary suggested that an ideal integration of electronic and mechanical tools could be achieved through  acquisitions.

To Gary, who was a fervent supporter of EDA, the ideal situation would be for EDA companies to acquire companies that offer mechanical and structural development tools.  And clearly this is an option.  But integrating mechanical design automation tools with electrical and electronic DA tools through corporate collaboration is also a possible solution.  By integration I do not mean building one tool that supports both electronic and mechanical design.  I mean creating a family of products that share data and are supported by one organization.  The centralized support is critical to avoid misunderstanding of problems that can arise from improper integration of tools.  I know at least three companies that already offer some levels of such integration: Ansys, Mathworks, and Mentor.

Ansys is an example of a company that started supporting system design with tools dealing with mechanical and physical problems and then that acquired companies dealing with electrical and electronic problems.  Today it offers integrated support to system designers and developers that span the entire product development sequence in various markets.

Mathworks is an example of a company that started out developing tools that spanned both physical and electronics development and worked with leading EDA tools providers to integrate its Simulink tool with additional EDA capabilities to create solutions without the need to acquire companies or develop tools itself.

In the automotive market Mentor has integrated its tools with third party tools to provide a multi-discipline development environment.  Its SystemVision multi-discipline development environment provides an integrated simulation opportunity to analyze both electronic and mechanical issues.

Clearly Gary’s proposed solution has additional benefits to the EDA industry.  For one it increases the revenue of the sector and it also decreases the dependence on solely electronics and semiconductors demand for its revenue.  At a time when the IoT sector is talked about as the major contributor to increased revenue, calmer voices are pointing out that most of the foreseen products are consumer products that do not require advanced technology.  But they require increased security and improved integration of electro/mechanical and software constituent parts.  The opportunity, then, is not to focus solely on improving support for leading edge process technologies, but to provide fail safe integration of hardware/software/mechanical portions of the products at a reasonable price point.  At this is something that will require a change in the growth plans for the EDA industry.

Veloce Power Application Enables Mentor/Ansys Collaboration

Wednesday, July 1st, 2015

Gabe Moretti, Senior Editor
One of the most interesting sessions for me at DAC was the luncheon that described the collaboration between Mentor and Ansys.  In general a large company collaborates with a much smaller one because a key customer requests it and has alternative solution in case the collaboration does not take place.  But Mentor and Ansys have relatively the same amount of yearly revenue, although Ansys is more diversified than Mentor and thus Mentor has greater EDA revenue than Ansys at present.

Power continues to be a primary concern for handheld and smart devices with high resolutions screens that require long battery life, and even wall-plugged equipment in a datacenter or in a network configuration needs to reduce operation costs. Using FinFET process technology reduces static leakage, yet dynamic power remains a challenge.

Since the acquisition of Apache, Ansys has increased its presence in the power analysis and management in the market, an area that is becoming a key part of the vast majority of electronic products.  But engineers could do little during emulation with respect to power analysis.  A new product from Mentor has made possible real-time transfer of power switching activity, via a Dynamic Read Waveform API, to power analysis tools replacing current file-based activity transfer methodology.

A new usage model for handheld and smart devices is driving a methodology shift in the way power is analyzed.  One primary driver in this shift is the fact that complex SoC designs are now verified using live applications that require booting the OS and running software applications on an emulator. It is more effective to use the power switching activity plot, generated during emulation, to pass real-time switching activity information to power analysis tools where potential power issues can be evaluated.

“The Veloce Power Application is a proof point to show that a new methodology that captures real power consumption during emulation and effectively passes that information to power analysis tools is more efficient.” said Eric Selosse, vice president and general manager of the Mentor Emulation Division.

“This collaboration addresses the challenges for designers of energy-efficient IP and SoC designs in various IoT verticals,” said Vic Kulkarni, Sr. vice president and general manager, RTL power business, at Apache division of ANSYS. “With our industry leading PowerArtist solution, we are delighted to be the premier partner in the Veloce Power Application ecosystem, and to work so closely with a technology leader in hardware emulation.”

IP Components Are EDA Tools

Friday, January 9th, 2015

Gabe Moretti, Senior Editor

It has been just about 25 years since the first IP product was licensed and yet there are still questions about the true nature of the IP industry.  A few years ago EDAC started providing figures for IP revenue, and that created a debate that to some extent continues today.  Is an IP company an EDA company?  Some say yes and some strongly object and prefer to define an IP company as a fabless semiconductor company.  Is there a correct definition of the industry that creates IP?  And which IP are we talking about?  EDAC is looking only at hardware IP, but of course there are many software IP products available.  What is IP?  The name itself is not very specific.  IP stands for Intellectual Property, but that covers anything that can be copyrighted, patented, or otherwise claimed to be property that cannot be freely copied, sold, or used without express permission from its creator.  It was not the intention of the creator of the term to cover all those items, but then marketing is a difficult if imprecise, job.

So to make things easier, let’s discuss only about the IP components representing hardware that are used by hardware designers in the design and development of hardware.  Are the producers and vendors of such products EDA companies?  To be sure some EDA companies develop and sell IP.  Cadence, Mentor, and Synopsys call themselves EDA companies and all generate revenue from licensing IP products.  ARM, the leading IP company, sells development software for its products that is just as sophisticated as tools sold by EDA companies, so is ARM an EDA company?

I would like to look at IP in a different light, a point of view I share with Lucio Lanza.  IP components are used by designers in the design and development of electronic products.  The EDA industry’s purpose is to develop and market tools used by designers to design and develop electronic products.  Ergo, IP is an EDA tool.  In fact engineers do not just integrate IP components in their designs.  They use IP in making tradeoff judgments regarding architecture, performance, development cost, and ultimately price of the product they are working on.  IP is indeed an EDA tool, so EDAC is correct in counting the revenue as an EDA industry revenue.

There is also a practical aspect to the argument.  One cannot separate IP revenue from the overall revenues of Cadence, Mentor, or Synopsys, just to take the big three into consideration, without those companies deciding to account for IP revenues as a separate profit center.  And why should they if IP is the same as EDA tools?

EDA in 2015: Something New and Something Old

Monday, December 1st, 2014

Gabe Moretti, Senior Editor

Every year I like to contact EDA companies to ask what they expect in 2015.  When I started working on this project I visualized one article that would offer the opinions of EDA industry leaders from many companies covering their expectations for the coming year.  As work progressed I found, as I should have expected, that the responses to my questions were much broader and in depth than could possibly be covered in one article.  Doing so would have resulted in such a long article that would have surpassed the time limits most engineers have to read a magazine, even a digital one.

So I decided to publish three articles in addition to this introductory blog.  The decision is based mostly on the amount of feedback I received, and in part by how stand-alone the input was.  It turns out that both Cadence and Mentor provided me with material that can be judged to be a contributed article, while the rest of the companies submitted contributions that could be grouped into an article, albeit one significantly longer than normal.  The articles will be published during this week, one article a day.

Designers, architects, and verification engineers will find worthwhile material in more than one article.  One subject that is receiving attention lately and that is not covered directly in the articles is Agile IC Methodology.  In truth Chi-Ping Hsu of Cadence talks about the issue in his article, but not in the terms of the conversation going on under the auspices of Sonics, Inc.  I am sure that I will write about Agile IC Methodology in 2015 so this subject will receive its due attention.

Verification and mixed/signal design are the subject that have received the greatest attention.  But it is important to acknowledge the underlying drivers for such attention: hardware/software co-design, and the use of third party IP.  These are the true technology drivers.  From a market point of view, automotive looms important.  This market has been developing for a few years and has now reached the point in which it can approach its full potential.  Distributed intelligence and “Thing to Thing” communication and co-operation is within the grasps of product developers.  The automobile is the first working implementation of the Internet of Things (IoT).  IoT is in everyone’s mind in our industry, and the intelligent automobile, even if such product does not really use the internet architecture in most instances, is often used as an example.  The IoT will certainly be a significant driver of our industry, but its growth ramp in 2015 will still be linear as we continue to understand what the hierarchical architecture should really look like.  At this point anything that could possibly generate data is seen as a good prospect, but soon the market will discover that much of the data may be interst9ing but it is not necessary, and in fact would just clutter one’s life.  As usual, customers’ demand will inject sense in the market.

In a time when all festivities seem to start two months before they actually occur let me be one of the firsts to wish all of you a productive and peaceful 2015.