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Posts Tagged ‘Power’

A Brief History of Verification

Thursday, March 2nd, 2017

Gabe Moretti, Senior Editor

This year’s DVCon is turning out to be very interesting.  It may be something that Jim Hogan said.  Jim insisted, in more than one panel, that we are at the cusp of a major change, an opportunity for startups that has a greater probability of revolutionary success than in the last few years in the area of verification and, I add, circuit design.

His observations got me thinking, reviewing my experiences in various aspects of verification I have been involved in.  What follow is my existential history of verification.

Logic is What Counts

When in 1968 I wrote my first logic simulator I only had to deal with a two states Boolean logic.  A node was either on or off.  Everything else about the circuit was not important.  It was not very long after that that things got more complex.  Now Boolean logic had three states, I and other verification engineers met the floating gate.  And then shortly thereafter memories became a real physical quantity in designs and four-state logic became the norm.  We had to know whether a bit was initialized in a deterministic manner or not.  From then on verification engineers’ major problem was the size of the circuit to be simulated and how efficient we could make the simulator so that run times were as short as possible.  And by the way this is still going on today, although for more complex reasons.

Enters Physics

As the size of transistors got smaller and smaller verification engineers found that physics grew in importance.  We no longer could assume that a circuit was well behaved in the physical domain, but had to worry about power, electromagnetic effects, and thermal characteristics.  Verification engineers had to understand physics, or, better yet, physics professionals had to join the ranks of verification engineers.

Today, thanks in part to logic synthesis, Boolean logic issues are well understood, and development work is focused on the physical characteristics of the circuit and, just to make things interesting, its immediate environment.  Todays’ complex problems deal with clock networks management and their interaction with power distribution and consumption that determines the functional state of the circuit.  How power transmission effect the nearby circuitry, how the current of electrons warms the device and how temperature impacts the probability that a transistor can maintain the state it is supposed to have are today’s issues.

Behavioral Scientists Find a New Job

There has been much talk at this year’s DVCon about safety and security, issues that are really behavioral and not about logic or physics.  During a lunch panel on Tuesday the importance of safety and security in complex systems, often employing diverse and distributed circuitry, was indicated as being the next important aspect of a system to verify.  Defense, automotive, and mobile applications were used as examples.  More than one panelist with Jim Hogan again assuming a leading role, spoke about the desirability of self-correcting systems.  If a safety failure occurred, or a security breach, the most desirable thing would be to have the circuitry prevent the occurrence or fix itself thus limiting the damage and the cost of repairs.   Verification engineers will have to deal with behavioral science in order to understand the danger, build a knowledge base of past incidents, and develop circuitry that will identify and prevent the faulty behavior in the future.  This, or course, requires that we can define what a good behavior is and what would signify a deviation from it.

Can We Do Better?

Now that I no longer develop verification tools, I think that both hardware and software developers have gotten lazy.  Transistors are now assumed to exist to the point that no one ever asks himself or herself “will this fit?” since the answer is “of course, and with transistors to spare”.  We design and develop complex circuits not just because they have to be but because they can be.

The amount of data produced by the various verification tools is so large that it is becoming impossible for a human to correlate all of it into a meaningful indication of the wellness and effectiveness of the design.  Tools to manage big data are required, especially when decisions must be made in the field during actual deployment.

And as transistors grow smaller and smaller in order to provide more of them every couple of years, we are unconsciously marching toward the boundary of Einstein’s space time environment to get closer and closer to quantum physics.  What will happen when one day we will be able to determine the state of a transistor or the trajectory of the electrons but not both at the same time?

I believe that it is time to go back in time and asks ourselves “ Is there another implementation that is simpler and uses fewer transistors?” the same way I used to ask “How can I make my program fit in 8K bytes of memory?”  Verification engineers must develop an efficiency measurement tool that warns design engineers when they are not efficient.  Not for the sake of elegance, but for the sake of simplicity.  Simplicity in circuit design means fewer physical problems and fewer behavioral problems.

The best business opportunity of this approach, of course, is in the area of IP.  Design, develop, and market the most efficient implementation of a function and, assuming you have some understanding of business management, you will be a successful entrepreneur.

Kilopass Unveiled Vertical Layered Thyristor (VLT) Technology for DRAMs

Wednesday, October 19th, 2016

Gabe Moretti, Senior Editor

Kilopass Technology, Inc., is a leader in embedded non-volatile memory (NVM) intellectual property (IP).  Its patented technologies of one-time programmable (OTP) NVM solutions scale to advanced CMOS process geometries. They are portable to every major foundry and integrated device manufacturer (IDM), and meet market demands for increased integration, higher densities, lower cost, low-power management, better reliability and improved security.  The company has just announced a new device that potentially allows it to diversify into new markets.

According to Charlie Cheng, Kilopass’ CEO, VLT eliminates the need for DRAM refresh, is compatible with existing process technologies and offers significant other benefits including lower power, better area efficiency and compatibility.  When asked the reason for this additional corporate direction Charlie replied: “Kilopass built its reputation as the leader in one-time programmable memories,” says Charlie Cheng, Kilopass’ chief executive officer. “As the next step on our roadmap, we examined many possible devices that would not need new materials or complex process flows and found this vertical thyristor to be very compelling.  We look forward to commercializing VLT DRAM in early 2018.”

VLT Overview

Kilopass’ VLT is based on thyristor technology, a structure that is electrically equivalent to a cross-coupled pair of bipolar transistors that form a latch. The latch lends itself to memory applications since it stores values and, as opposed to current capacitor-based DRAM technology, does not require refresh. The thyristor was first invented in the 1950s and several attempts have been made to use it for the SRAM market without success.  Kilopass’ VLT is the realization of DRAM requirements based on implementing the thyristor structure vertically.

Since VLT does not require complex performance- and power-consuming refresh cycles, a VLT-based DDR4 DRAM lowers standby power by 10X when compared to conventional DRAM at the same process node. Furthermore, VLT requires fewer processing steps and is designed to be built using existing processing equipment, materials and flows.

The VLT bitcell operations and silicon measurement were completed in 2015 and shown to have excellent correlation to Kilopass’ proprietary ultra-fast TCAD simulator that is one hundred thousand times faster than a traditional TCAD simulator. The TCAD simulator enables Kilopass to predict the manufacturing windows for key process parameters, and optimize the design for any given manufacturing process.  A full macro level test chip was taped-out in May and initial silicon testing is underway.
Industry Perspective

The $50B DRAM market is being driven by strong demand in the server/cloud computing market as mobile phone and tablet market growth are slowing down and computing is moving increasingly to the cloud. The outlook for DRAM growth remains strong. In a report published in 2015, IC Insights forecasts DRAM CAGR of 9% over the period from 2014 – 2019. This growth rate shows DRAM growing faster than the total IC market.

Servers and server farms consume a tremendous amount of energy with memory being a major contributor. In an ideal world, the current generation of 20 nanometer (nm) DRAM would migrate to sub-20nm processes to deliver even lower power.

Current DRAM technology is based on the 1 transistor, 1 capacitor. The (1T1C) bitcell is difficult to scale since the smaller transistors exhibit more leakage and the smaller capacitor structure has less capacitance, resulting in the need to reduce the time between refresh intervals. Up to 20% of a 16Gb DDR DRAM’s raw bandwidth will be lost due to the increased frequency of refresh cycles, a negative for multi-core/multi-thread server CPUs that must squeeze out every bit of performance to remain competitive. The DRAM industry is in a quandary trying to increase memory performance while reducing power consumption, a tough challenge given the physics at play with the current 1T1C technology. In order to address the need for lower power consumption a new DRAM technology and architecture is needed.

Kilopass stated that its initial target markets include “PCs” and servers. I am of the old school and associate the term “PC” to personal computers.  But Kilopass uses the term to mean Portable Computing Devices so it is talking about a different market.  Kilopass expects to have test silicon by early 2017 that will confirm performance of the new VLT DRAM technology and manufacturability.   Kilopass has two primary reasons to announce the new technology over one year in advance of product delivery.  First the company is in the IP business, so it is giving itself time to look for licensees.  Secondly it thinks that the DRAM market has been stuck at 20nm. Adoption of new technology takes time, though VLT has been shown to be manufacturable. This is the right time to alert the market that there are alternative solutions, allowing time for investigation of this new technology.   Market penetration of new technology is not always assured.  Wide acceptance almost always requires a second source, especially with something so new as the VLT device.  Memories play a critical role cloud computing but a far smaller one in PC since power consumption in PC is not a widespread issue.

Cadence Introduced Tensilica Vision P5 DSP

Thursday, October 8th, 2015

Gabe Moretti, Senior Editor

DSP devices are indispensable in electronic products that deal with the outside environment.  Wheter one needs to see, to touch, or in any way gather information from the environmanet, DSP devices are critical.  Improvements in their performance characteristics, therefore, have a direct impact not only on the capability of a circuit, but more importantly, on its level of competitiveness.  Cadence Design Systems has just announced the Cadence Tensilica Vision P5 digital signal processor (DSP), which it calls its flagship high-performance vision/imaging DSP core. Cadence claims that the new imaging and vision DSP core offers up to 13X performance boost, with an average of 5X less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP.

Jeff Bier, co-founder and president of Berkeley Design Technology, Inc. (BDTI) noted that: “There is an explosion in vision processing applications that require dedicated, efficient offload processors to handle the large streams of data in real time.  Processor innovations like the Tensilica Vision P5 DSP help provide the backbone required for increasingly complex vision applications.”

The Tensilica Vision P5 DSP core includes a significantly expanded and optimized Instruction Set Architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems.

“Imaging algorithms are quickly evolving and becoming much more complex – particularly in object detection, tracking and identification,” stated Chris Rowen, CTO of the IP Group at Cadence. “Additionally, we are seeing a lot more integrated systems with multiple sensor types, feeding even more data in for processing in real time. These highly complex systems are driving us to provide more performance in our DSPs than ever before, at even lower power. The Tensilica Vision P5 DSP is a major step forward to meeting tomorrow’s market demands.”
Modern electronic systems architecture threats hardware and software with the same amount of attention.  They must balance each other in order to achieve the best possible execution while minimizing development costs.  The Tensilica Vision P5 DSP further improve the ease of software development and porting, with comprehensive support for integer, fixed-point and floating-point data types and an advanced toolchain with a proven, auto-vectorizing C compiler. The software environment also features complete support of standard OpenCV and OpenVX libraries for fast, high-level migration of existing imaging/vision applications with over 800 library functions.

The Tensilica Vision P5 DSP is specifically designed for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates. As such, it allows off-loading vision and imaging functions from the main CPU to increase throughput and reduce power. End-user applications that can benefit from the DSP’s capabilities include image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction.

The Tensilica Vision P5 DSP is based on the Cadence Tensilica Xtensa architecture, and combines flexible hardware choices with a library of DSP functions and numerous vision/imaging applications from our established ecosystem partners. It also shares the comprehensive Tensilica partner ecosystem for other applications software, emulation and probes, silicon and services and much more.  The Tensilica Vision P5 core includes these new features:

  • Wide 1024-bit memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing
  • Up to 4 vector ALU operations per cycle, each with up to 64-way data parallelism
  • Up to 5 instructions issued per cycle from 128-bit wide instruction delivering increased operation parallelism
  • Enhanced 8-,16- and 32-bit ISA tuned for vision/imaging applications
  • Optional 16-way IEEE single-precision vector floating-point processing unit delivering a massive 32GFLOPs at 1GHz

The eSilicon IP MarketPlace: Easy and Quick Integration of IP in Your Design

Monday, December 8th, 2014

Gabe Moretti, Senior Editor

The eSilicon IP MarketPlace product is simply what every IP vendor would like to have.  I am not a practicing designer, yet I found the environment easy to navigate, full of useful information, and an evaluation tool that takes one directly to selecting the correct IP for the target design.  Once I logged on and started my “test drive”, I felt instant gratification, as my commands produced data I could process readily, or information I could evaluate right away.  And the best thing is that it is free.

In my career as an editor I have very seldom started a product launch review so positively, but it is my job to give the correct information and this product is special.  The reason, I think, is because it bridges the gap between what one can learn from a good data sheet and what one finds when the GDS tape is generated.  In between there is a lot of work, and work that gets exponentially harder as we move to the latest process nodes technology.  And don’t even try to evaluate the same IP fabricated by two different foundries without this tool!  It would just take too long.

The IP MarketPlace environment helps users avoid complicated paperwork; find which memories will best help meet their chip’s power, performance, and area (PPA) targets that apply to your specific requirements, easily isolate key data, and perform vital “what-if” analysis.

The IP MarketPlace environment contains all eSilicon-developed IP across multiple foundries and technologies:

  • Memory compilers, including 28HPM TCAMs, four-port register files and two-port asynchronous register files
  • General-purpose I/O libraries from 16nm to 180nm
  • Specialty I/O libraries from 16nm to 180nm, including 1.8V/3.3V LVCMOS I/Os

Once a designer has chosen a memory type, IP Marketplace provides immediate answers with pre-loaded data for eSilicon memory compilers and I/O libraries.  Engineers can:

  • Generate dynamic, graphical analyses of power, performance and area (PPA) data
  • View data graphically, in table format, or download it to Microsoft Excel
  • Build and download a complete chip memory subsystem
  • Generate and download IP front-end views
  • Make changes over time and pay for the IP when ready to tape out (in the next release the payment will be made on-line without leaving the environment)

“We wanted to simplify the comparison of results across multiple technologies, architectures and other characteristics and take the guesswork out of hitting PPA targets,” said Lisa Minwell, eSilicon’s senior director of IP product marketing. “This goes much, much deeper than IP portals that serve as IP catalogs. Using the IP MarketPlace environment, users can download front-end views, run simulations in their own environments, then come back to purchase the back-end views of the IP and I/Os that best fit their design.”

To kick the tires go to http://www.esilicon.com/custom-ip/ip-marketplace.  I bet you will be convinced.  The only drawback I found is that it may take up to 24 hours before you get access to the tool since they email you back your login information almost immediately but then you have to wait for another email that gives you access to the site where you can choose an IP and start working with it.  So the first time is not immediate gratification but, as I said, the wait is worth it.