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Grant Pierce Named BoD Chair of the ESD Alliance

Tuesday, February 21st, 2017

Gabe Moretti, Senior Editor

The ESD Alliance (ESDA) has elected Grant Pierce (CEO of Sonics) as its Chairman of the Board a few weeks ago.  Grant is only the second Chair that is not a high level executive of one of the three big three EDA companies to hold the title, and the first since the organization, formerly EDAC renamed itself.  During the EDAC days it was customary for the CEOs of Cadence, Mentor and Synopsys to pass the title among themselves in an orderly manner.  The organization then reflected the mission of the EDA industry to support the development of hardware intensive silicon chips following Moore’s Law.

Things have changed since then, and the consortium responded by first appointing a new executive director, Bob Smith, then changing its name and its mission.  I talked with Grant to understand his view from the top.

Grant Pierce, Sonics CEO

Grant pointed out that: “We are trying to better reflect what has happened in the market place, both in terms of how our customers have developed further in the world of system on chip and what we have seen in the development of the EDA world where today the IP offerings in the market, both those from independent companies but also those from EDA companies are critical and integral to all the whole ecosystem for building today’s modern chips.”

Grant pointed out that ESDA has expanded its focus and has embraced not only hardware design and development but also software.  That does not mean, Grant pointed out, that the EDA companies are loosing importance but instead they are gaining a seat at the table with the software and the system design community in order to expand the scope of their businesses.

From my point of view, I interjected, I see the desired change implemented very slowly, still reacting to and not anticipating new demands.  So what do you think can happen in the next twelve months?

“From an ESDA point of view you are going to see us broadening the membership.” answered Grant.  ”We are looking to see how we can expand the focus of the organization through its working groups to zero-in on new topics that are broader than the ones that are currently there.  Like expanding beyond what is a common operating system to support for example.  I think you will see at a minimum two fronts, one opening on the software side while at the same time continuing work on the PPA (Power, Performance, Area) issues of chip design.  This involves a level of participation from parties that have not interacted this organization before.”

Grant believes that there should be more emphasis on the needs of small companies, those where innovation is taking place.  ESDA needs to seek the best opportunity to invigorate those companies.  “At the same time we must try to get system companies involved in an appropriate fashion, at least to the degree that they represent the software that is embedded in a system” concluded Grant.

We briefly speculated on what the RISC 5 movement might mean to ESDA.  Grant does not see much value for ESDA to focus on a specific instruction set, although he conceded that there might be value if RISC 5 joined ESDA.  I agree with the first part of his judgement, but I do not see any benefit to either party, or the industry for that matter, associated with RISC 5 joining ESDA.

From my point of view ESDA has a big hurdle to overcome.  For a few years, before Bob Smith was named executive director, EDAC was somewhat stagnant, and now it must catch up with market reality and fully address the complete system issue.  Not just hardware/software, but analog/digital, and the increased use of FPGA and MEMS.

For sure, representing an IP company gives Grant an opportunity to stress a different point of view within ESDA than the traditional EDA view.  The IP industry would not even exist without a system approach to design and it has changed the way architects think when first sketching a product on the back of an envelope.

EDA has not been successful at keeping its leaders

Wednesday, January 4th, 2017

Gabe Moretti, Senior Editor

I have often wondered why when a larger EDA company acquires a smaller one, the acquired CEO ends up, in a relatively short time, leaving and either joining a new start-up or a venture capital firm.  It seemed to me that that CEO thought enough of the buyer to predict his (or hers) employees and product(s) would prosper in the new environment when accepting to be acquired.  So, why leave?  It could just not be a matter of strong contrasting personalities.  I think I found the answer over the Christmas break.

I read the book “Skunk Works” by Ben R. Rich.  The book is a factual history of development projects that were carried out while Ben was first there as an employee and eventually its leader.  During his years at the Skunk Works Mr. Rich was part of the exceptional successes of the U-2 and SR-71 spy planes, and of the F117A stealth bomber.  All those projects were run independently of corporate overseers, used a comparatively small dedicated team, and modified the project when necessary to achieve the established goal.

Two major points made in the book apply both to the EDA industry and to industry in general.  First “Leaders are natural born: managers must be trained” and second “There is no substitute for astute managerial skill on any project”.

Many start-up CEOs are born leaders and do not fit well within an organization where projects are managed in a bureaucratic manner using a rigid reporting structure.  An ex-CEO will soon find such work environment counter-productive.  Successful projects need to react quickly to changing realities and parameters.  Often in the life of a project the team discovers new opportunities or new obstacles that come to light because of the work being done.  The time spent explaining and justifying the new alternative will impact the success of the project, especially if the value of the presented alternative is not fully understood by top executives or the new managers do not understand the new corporate politics.

I think that the best use of an acquired CEO is to allow him or her to continue to be an entrepreneur within the acquiring company.  This does not mean to use his talent to continue to lead the just acquired team. He can look for new opportunities within his area of expertise and possibly build a new team that will produce a new product.  In this way the acquiring company increases its ROI form the acquisition, even at the cost of increased compensation to both the CEO and his new team at the successful completion of their work.

In general Synopsys has managed to retain acquired CEOs, while Cadence has not.

The behavior in the EDA industry, with very few well known exceptions, has been to seek a quick reward through an acquisition that will satisfy financially both the venture capitalists and the original start-up team.  Once the acquisition price is monetized, many people leave the industry seeking to capitalize on their financial gains in other ways.  Thus the EDA industry must grow through the entrance of new people with new ideas but little if any experience in the industry.  The result is many academic brilliant ideas that result in failed start-ups.  Individuals with brilliant ideas are not usually good leaders or managers, and good managers do not generally possess the creativity to conceive a breakthrough product.

In its history the EDA industry has paid the price of creating both leaders and excellent managers, but has yet to find a way to retain them.  Of course there are a few exceptions, nothing is ever black and white, but the exceptions are few.  It will be interesting to see, after a couple of years, how Siemens will have handled the Mentor Graphics acquisition.  Will Mentor’s creativity improve?  Will the successful team remain?  Will they use the additional resource in an entrepreneurial manner, or either leave or adjust to a more relaxed big company life?

ARC Processor summit in Santa Clara

Tuesday, August 30th, 2016

Gabe Moretti, Senior Editor

Synopsys is holding its second ARC Processor summit on September 13 at the Santa Clara Marriott.

The full day conference will open at 9:00 for on-site registration.  Synopsys will provide complimentary parking to attendees.  To see the full program please go to:

http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/arc-processor-summit-2016.aspx

The ARC processor family comprises a number of versions of the MCU adapted to specific applications as well as a general purpose version.  From my point of view, the ARC processor family offers two major advantages to its customers: the availability of a large and tested IP family directly from Synopsys, and Synopsys leading edge rapport with many foundries, including all the important ones.

The day’s events are divided into three tracks: Hardware, Software, and Embedded Vision.

Linley Gwennap, The Linley Group, will deliver the keynote.  The title is: “IoT Standards Wars: Caught in the Middle?”

Given the number of devices and the differences of applications, it is extremely important to arrive quickly to a set of agreed upon standards that can support this variety and still offer robustness, flexibility and security.

The day will conclude with a demo session and networking opportunity from 5:30 to 7:00.

The ARM – Softbank Deal: Heart Before Mind

Tuesday, July 19th, 2016

Gabe Moretti, Senior Editor

If you happen to hold ARM stock, congratulation, you are likely to make a nice profit on your investment.  SoftBank, a Japanese company with diversifies interests, including Internet provider, has offered to purchase ARM for cash by tendering $32.4 billion dollars.  SoftBank is a large company whose latest financial result show that it made a profit of $9.82 before interest payments and tax obligations.

ARM, on the other hand, reported for 2015 fiscal year revenue of $1.488.6 billion with a profit of $414.8 million and an operating margin of 42%.  This is a very healthy operating margin, showing a remarkable efficiency by all aspects of the company.  So, there is little to improve in the way ARM operates.

What seems logical, then is that SoftBank expects a significant increase in ARM revenue after the acquisition, or an effect on its profit due to ARM’s impact on other parts of the company.  ARM profit for 2015 were 414.8 million British sterling and the revenue in sterling was 968.3 million for a ratio of 42.8%.  Let’s assume that SoftBank instead invested all of the $32.4 billion and obtained a 5% return or $1.62 billion per year.  To obtain the same result from the ARM acquisition it would mean that ARM must generate a profit of 3.9 times what it generated in 2015.  This is a very large increase since if we assume that all other financial ratios stay the same revenue would have to be a little over $5.5 billion. Yet, using the growth of 15% realized between 2014 an2015 for every year between 2015 and 2020 we “only” achieve a $2,913.6 billion mark.  And keeping the growth ratio constant as revenue increase gets harder and harder since it means a large increase every year.

So the numbers do not make sense to me.  I can believe that ARM could be worth $16 billion, but not twice as much.  And here is another observation.  I have read in many publications that financial analysts expect the IoT market to be $20 billion by 2020.  Assuming that the SoftBank investment, net of interest charges, returns 5% per year in 2020, it would mean that ARM’s revenue would be $5.5 billion or over 25% of TAM (Total Available Market).  This, I consider impossible to achieve, simply because the IoT market will be price sensitive, thus opening ARM to competition by other companies offering competitive microcontrollers.  SoftBank cannot possibly believe that Intel will go away, or that every person will own three cell phones each, or that Google will use only ARM processors in its offerings, or even that IP companies like Cadence and Synopsys will decide to ignore the IoT market.

I am afraid that the acquisition marks the end of ARM as we know it.  It will be squeezed for revenue and profit like it has never been before and the quality of its products will suffer.

DAC Official Results Are In

Thursday, June 23rd, 2016

Gabe Moretti, Senior Editor

Have already covered DAC in a previous blog, but a couple of days ago I received an email from Michelle Clancy, 53rd DAC PR/Marketing Chair, reporting on the conference attendance.  I have additional observations on the Austin conference as a result of the release.

As far as I am concerned the structure of the release was poor.  Readers were guided to consider the overall attendance numbers which was quite small. The increment in overall badges between the 2013 Austin DAC and this year is an increase of 125 badges.  That is an increase of 2.1% significantly less that the increase in the revenue of the EDA industry in the same span of time.  And in addition we have witnessed the growth of related industries who have a presence in and around Austin such as embedded systems and IoT.

What should be underlined is the difference between conference attendees badges from 2013 and 2016.  There were 719 more conference badge this year, while the free “I LOVE DAC” passes were down 564 for the same comparison.  To me this are the important data.  It means that there were fewer “tire kickers” who collect souvenirs and more technical program or tutorial attendees than in 2013.  These are the numbers that indicate success, but the press release did not dwell on them.

I also find it telling that the quote in the release from Howard Pakosh, managing partner of TEKSTART, which provides interim sales, marketing and business development capital to high-tech entrepreneurs, observes “The people we’ve been talking to in Austin are actually looking for information and solutions; they’re not just here because it’s an easy commute from Silicon Valley.”  Obviously Mr. Pakosh finds it a waste of time to exhibit in San Francisco.

My experience on the exhibit floor was different.  The fact that Synopsys chose to send fewer PR and marketing persons to Austin was a negative point for me.  It was difficult to find the right person to discuss business with.  The company also did not have their usual press/analysts dinner and this is unfortunate since their new message “silicon to software” was not well presented on the floor.  I left the conference without understanding the message, especially since I was told in my meeting with corporate marketing that their effort was to promote products from Coventry and Codenomicon to markets outside the electronics business.  Are those products the “software” they are talking about?  What about embedded software for all sort of applications, including those who use their ARC processors?

Cadence and Mentor booths were better staffed, at least I met all the professionals I needed to meet. It is of course time that Cadence realizes that “The Denali Party” does not take the place of a serious dinner with press and analysts.  The Heart of Technology party is a better choice if one wants music and drinks and it supports a good cause.  I go to DAC to do business, not to drink cheap drinks and fight for food in a crowded buffet line.

It is of course expected that the technical program offered by DAC covers leading edge issues and opportunities.  This part of DAC was well organized and run.

If the DAC committee sees the need to defend the choice of Austin as the venue for the conference, then why use the venue next year?  Clearly the have determined that Austin is a viable location.  I for one, did enjoy Austin as a host city and found the convention hall pleasant and well equipped.  Of course the distance between both sessions and exhibits to the press room was not at all convenient, but I do understand that the press room location was chosen because it allowed the building of the necessary temporary meeting rooms.

Custom Compiler Shortens Layout of FinFET Circuits

Wednesday, March 30th, 2016

Gabe Moretti, Senior Editor

Synopsys has made a break from constraints driven layout and introduced a new layout system that, according to the company, allows engineers to work in a visual manner. “Legacy custom design tools have not kept pace with the exponential growth in design complexity,” said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. “In particular, the growing number and complexity of FinFET design rules pose significant challenges for layout designers. Custom Compiler’s innovative assistants enable designers to address the most difficult layout challenges while significantly improving FinFET design productivity.”

The new tool is especially efficient when doing FinFET layout since it allows engineers to stack transistors in a visual manner while at the same time conserving the connectivity, thus saving hours of work.  Developing visually-assisted automation technologies that speed up common design tasks reduces iterations and enables reuse.

Custom Compiler Assistants, pictured in the figure above, are productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler provides four types of assistants: Layout, In-Design, Template and Co-Design.

  • Layout Assistants speed layout with visually-guided automation of placement and routing. The router is ideal for connecting FinFET arrays or large-M factor transistors. It automatically clones connections and creates pin taps. The user simply guides the router with the mouse and it fills in the details automatically. The placer uses a new innovative approach to device placement. It allows the user to make successive refinements, offering placement choices but leaving the layout designer in full control of the results—without requiring any up-front textual constraint entry.
  • In-Design Assistants reduce costly design iterations by catching physical and electrical errors before signoff verification. Custom Compiler includes a built-in design rule checking (DRC) engine, which is extremely fast and can be active all the time. In addition to the DRC engine, electromigration checking, and resistance and capacitance extraction are all natively implemented in Custom Compiler. Custom Compiler’s extraction is based on Synopsys’ StarRC engine.
  • Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistant’s placer and router. They intelligently recognize circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler comes pre-loaded with a set of built-in templates for commonly used circuits, such as current mirrors, level shifters and differential pairs.  Users can add more templates that are developed for their design styles as they are created and verified.
  • Co-Design Assistants combine the IC Compiler place and route system and Custom Compiler into a unified solution for custom and digital implementation. Users can freely move back and forth between Custom Compiler and IC Compiler, using the commands of each to successively refine their designs. With the Co-Design Assistants, IC Compiler users can perform full custom edits to their digital designs at any stage of implementation. Likewise, Custom Compiler users can use IC Compiler to implement digital blocks in their custom designs. The lossless, multi-roundtrip capability of the Co-Design Assistants ensures that all changes are synchronized across both the digital and custom databases.

Although Custom Compiler takes advantage of knowledge developed from existing Synopsys tools, it is not only a new product but a new approach to layout that fits well with FinFET use.  “As the leader in analog/mixed-signal semiconductor IP, our team has been exposed to FinFET related design challenges very early in the foundry process development cycle,” said Joachim Kunkel, executive vice president and general manager of the Solutions Group at Synopsys. “We asked the Custom Compiler development team to focus on improving FinFET layout productivity because we saw large increases in the layout effort across a wide range of IP development projects, from standard cells to high-performance SerDes. Custom Compiler’s Layout Assistants allowed us to implement a novel layout methodology that reduces the time of many layout tasks from hours to minutes.”

Synopsys’ Relaunched ARC Is Not The Answer

Wednesday, October 14th, 2015

Gabe Moretti, Senior Editor

During the month of September Synopsys spent considerable marketing resources relaunching its ARC processor family of products by leveraging the IoT.  First on September 10 it published a release announcing two additional versions of the ARC EM family of deeply embedded DSP cores.  Then on September 15 the company held a free one-day ARC Processor Summit in Santa Clara and on September 22 issued another press release about its involvement in IoT again mentioning the embARC Open Software Platform and ARC Access Program.  It is not clear that ARC will fare any better in the market after this effort than it did in the past.

Background

Almost ten years ago a company called ARC International LTD designed and developed a RISC processor called Argonaut RISC Core.  Its architecture has roots in the Super FX chip for the Super Nintendo Entertainment System.  In 2009 Virage Logic purchased ARC International.  Virage specialized in embedded test systems and was acquired by Synopsys in 2010.  This is how Synopsys became the owner of the ARC architecture, although it was just interested in the embedded test technology.

Since that acquisition ARC has seen various developments that produced five product families all within the DesignWare group.  Financial success of the ARC family has been modest, especially when compared within the much more popular product families in the company.  The EM family is one of the five product families where the two new products reside.  During this year’s DVCon, at the beginning of March I had an interview with Joachim Kunkel, Sr. Vice President and General Manager of the Solutions Group at Synopsys who is responsible among other things of the IP products.  We talked about the ARC family and how Synopsys had not yet found a way to efficiently use this core.  We agreed that IoT applications could benefit from such an IP especially if well integrated with other DesignWare pieces and security software.

The Implementation

I think that the ARC family will never play a significant part in Synopsys revenue generation, even after this last marketing effort.

It seems clear to me that the IoT strategy is built on more viable corporate resources than just the ARC processor.  The two new cores are the EM9D and EM11D which implement an enhanced version of the ARCv2DSP instruction set architecture, combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimizing power consumption.  Synopsys claims that the cores are from 3 to 5 times more efficient than the two previous similar cores, but the press release specifically avoids comparison with similar devices from other vendors.

When I read the data sheets of devices from possible competitors I appreciate the wisdom to avoid direct comparison.  Although the engineering work to produce the two new cores seems quite good, there is only so much that can be done with a ten years old architecture.  ARC becomes valuable only if sold as part of a sub-system that integrates other Synopsys IP and security products owned by the company.

It is also clear that those other resources will generate more revenue for Synopsys when integrated with other DSP processors from ARM, Intel, and may be Apple or even Cadence.  ARC has been neglected for too long to be competitive by itself, especially when considering the IoT market.  ARC is best used at the terminals or data acquisition nodes.  Such nodes are highly specialized, small, and above all very price sensitive.  A variation of few cents makes the difference between adoption or not.  This is not a market Synopsys is comfortable with.  Synopsys prefers to control by offering the best solution at a price it finds acceptable.

Conclusion

The ARC world will remain small.  Synopsys mark on the IoT will possibly be substantial but certainly not because of ARC.

Gary Smith’s DAC presentation: The Changing Landscape

Friday, June 26th, 2015

Gabe Moretti, Senior Editor

Since a couple of weeks have passed I have had time to think about the contents of the Sunday evening presentation by Gary Smith.  Gary touched many subjects but two in particular gave me reason to ponder.  The first one was his comment on the IP industry and the second his view on Synopsys expansion.

The IP Industry

Gary stated that revenue for IP products will first level off and then diminish in the period up to 2019.  This statement generated incredulous response from the audience.  In the time set aside for questions Gary stated that the reason for the decline was the market saturation for products like Synopsys DesignWare.

He said that small IP modules were now commodities that are free, or practically free, and that the only source of IP revenue will be IP subsystems.  By itself the statement is true, but I think that Gary missed the larger picture.  IP subsystems are growing in sophistication and now contain both hardware and firmware modules.  Their complexity will increase, not decrease, and with it the price they can command.  The projected expansion of IoT products also means a growing use of IP subsystems, thus a very large growth in the number of licenses sold.

In addition the sophistication of the subsystems require more powerful development tools to integrate the IP and debug the final system.  ARM, for example has just introduced a very sophisticated development environment.  The new IP tooling suite comprises Socrates DE, CoreSight Creator and CoreLink Creator. Additionally, CoreLink Creator will easily configure and help implement the new CoreLink NIC-450 Network Interconnect, the follow-on to the widely-adopted CoreLink NIC-400.  See my article at: http://chipdesignmag.com/sld/blog/2015/06/04/new-arm-ip-tooling-suite-reduces-significantly-soc-integration-time/.

How is the revenue generated by this new tool, and those likely to appear on the market by competitors, to be counted?  Clearly the revenue would not exist if the IP was not purchased and used.  So, I think, tools specifically used for IP, should be counted in the IP market, not in the general EDA tools markets.  In addition the firmware sold with or for IP should not be counted in the embedded software column, but in the IP column.  IP revenue will grow, it is just a matter how it will be counted.

Synopsys’s Growth

Gary observed that Synopsys was growing through acquisitions in niche markets with the intent to dominate those markets.  I think this view is too narrow.  To be sure Synopsys acquires companies that have a significant opportunity to grow, but the reason for the acquisitions is not “just” diversification.  If one steps back and looks at the system level, and not just at the electronic hardware level, one finds, or at least I find, that Synopsys is looking at the requirements of systems in  the near future and is obtaining the tools to be able to satisfy them as a company.  Security is an important especially with respect to software attacks.  The acquisition of Codenomicon addresses the robustness of developed software.  The earlier acquisition of Coverity is fundamentally in the same direction.  Gary is correct that both acquisitions bring Synopsys in the larger market of software development outside of EDA, but they also strengthen the corporate position within EDA.  The same can be said of the Optical Solution Group grown entirely by acquisition of non EDA companies.  My point is that Synopsys is becoming a true system company, not “just” an EDA company.

Synopsys to Acquire Codenomicon

Wednesday, April 22nd, 2015

Gabe Moretti, Senior Editor

After what many thought was a diversion of focus when Synopsys acquired Coverity, the company is making another bold move with the announced acquisition of Codenomicon

Based in Finland, Codenomicon is well-known and highly respected in the global software security world with a focus on software embedded in chips and devices.

The official Synopsys release states: “The additional talent, technology and products will expand Synopsys’ presence in the software security market segment and extend the Coverity quality and security platform to help software developers throughout various organizations quickly find and fix security vulnerabilities and protect applications from security attacks.”

Fine thought and certainly true.  But looking at the security problems, those already found and those yet to be written about, in the IoT architecture, I think that Synopsys should not minimize the impact that the technologists at Codenomicon will have on the EDA market.

“Businesses are increasingly concerned about the security of their applications and protecting customer data. Adding the Internet of Things to the mix increases the complexity of security even further. During the past 15 months, the world was hit by major security breaches such as Heartbleed, Shellshock, etc.,” said Chi-Foon Chan, president and co-CEO of Synopsys. “By combining the Coverity platform with the Codenomicon product suite, Synopsys will expand its reach to provide a more robust software security solution with a full set of tools to help ensure the integrity, privacy and safety of an organization’s most critical software applications.”

Codenomicon’s customer base includes some of the world’s leading organizations in telecommunications, finance, manufacturing, software development, healthcare, automotive and government agencies.  But as part of Synopsys Codenomicon’s solutions deliver a more comprehensive security offering for the software development lifecycle by adding its Defensics tool for file and protocol fuzz testing, and its AppCheck tool for software composition analysis and vulnerability assessment to the embedded software used in electronics systems.

The Codenomicon Defensics tool used to discover the Heartbleed bug automatically tests the target system for unknown vulnerabilities, helping developers find and fix them before a product goes to market. It is a systematic solution to make systems more robust, harden them against cyber-attacks and mitigate the risk of 0-day vulnerabilities. The Defensics tool also helps expose failed cryptographic checks, privacy leaks or authentication bypass weaknesses. The Defensics tool is heavily used by buyers of Internet-enabled products to validate and verify that procured products meet their stringent security and robustness requirements.

The Codenomicon AppCheck tool adds software composition analysis (SCA) capabilities to the Coverity platform, helping customers reduce risks in third-party and open source components. When using the AppCheck tool, customers are able to obtain a software bill of materials (BOM) for their application portfolios, and identify components with known vulnerabilities.

FPGA Prototyping Could Become Mainstream Again

Thursday, February 12th, 2015

Gabe Moretti, Senior Editor

Since the very early days of ASIC design engineers have prototyped their ASIC development using FPGA devices in order to debug and verify the design.  The advantage is that the Device Under Test (DUT) runs at speeds that are much greater than those achievable with traditional simulation and in most cases equal or nearly equal those of the actual device.  This is particularly useful in debugging the product’s  firmware, but it also helps in various hardware situations.

FPGA prototyping is not just a thing of the past, before the introduction of emulators, it is a technique used today by many development teams.  Given the imminent development and introduction o a large number of small systems in the IoT architecture, I expect that there will be even more use of FPGA prototyping.  I asked the input of three representatives of EDA companies to get a better picture of the state of affairs.  One, Zibi Zalewski, General Manger of the Hardware Products Division at Aldec, represents the views of what I consider a middle size vendor, while Troy Scott, Product Marketing Manager at Synopsys represent the view of a large company that has a group dedicated explicitly to supporting FPGA prototyping of ASIC designs.  Frank Schirrmeister, Group Director for Product Marketing of the System Development Suite at Cadence,represents a company that competes for the number one position in the emulation and acceleration tools market.

Due to the length of the resulting article I chose to publish the three contributions as separate articles, and to group them herein my blog to give you, the reader, additional flexibility in covering the topic.

A Historical Approach

Zibi reviewed FPGA prototyping from an historical point of view.  He reminisced about his days as a development engineer and compared the requirement at that time with the development environment available today.  You can read his contribution at: http://chipdesignmag.com/sld/blog/2015/02/12/asic-prototyping-with-fpga/.

Using FPGA Prototyping for Faster System Validation

Synopsys has always been focused on the design and development of semiconductor devices since its inception, and has entered the market of FPGA based designs mostly in order to support ASIC prototyping.  You can read what Troy Scott sent me at this address: http://chipdesignmag.com/sld/blog/2015/02/12/asic-prototypes-take-the-express-lane-for-faster-system-validation/.

A Prototyping with FPGA Approach

Frank Schirrmeister provided a view of prototyping that frames it within the present efforts to decrease development time, the so called “shift left” approach or the recently proposed Agile IC Methodology.  You can read his thoughts here: http://chipdesignmag.com/sld/blog/2015/02/12/a-prototyping-with-fpga-approach/.

Conclusion

Although some may think that FPGA prototyping is a methodology that has seen its prime, the focus on IoT architecture, which use a large number of small, focused, systems, will revive this development method, since, in many cases, companies will be able to avail themselves of a fixed general purpose control subsystem and a function based data acquisition subsystem.  I in fact, envision development systems available fr purchase that offer a control and data analysis standard system and allow designers to include the sensor and circuitry specific to the function to generate a complete FPGA based prototyping environment.

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