The Week In Review: Feb. 10
Japan’s SoC market consolidates; Cadence collaborates with Samsung; Synopsys wins CSR deal; eSilicon licenses Avago SerDes cores; Methodics rolls out new IP version control.
"Job's Law makes sense - its about the user experience and this is how Apple creates end user value and loyalty" - Jack Browne

Deep Insights for Chip Architects and Engineers
Japan’s SoC market consolidates; Cadence collaborates with Samsung; Synopsys wins CSR deal; eSilicon licenses Avago SerDes cores; Methodics rolls out new IP version control.
Substrate biasing; crash dummies; case-splitting; pending unemployment; analog models; green cars.
Mentor boosts PCB tool functionality; Cadence posts strong earnings, solid outlook; Sonics teams with Tensilica.
Last of three parts: Faster derivatives; differentiation that matters; standards; multivendor tools vs. single-vendor integration; tradeoffs in stacked die.
Third-party IP, increased complexity, parasitic effects and software are making the verification challenge more difficult. Can this be fixed?
Manufacturing limitations and challenges increasingly will dictate what happens in IC design; more collaboration will be required across the supply chain.
Computers that are always ready, smart enough to anticipate what you want, aren’t science fiction anymore. But they do change the definition of a system.
Moving data will require significant infrastructure improvements; available wireless spectrum remains an issue.
What’s available, what’s missing, and what’s in development, and how models are being used inside STMicroelectronics.
Complexity, time-to-market demands and runaway costs are raising pressure for creating new standards, but working groups are getting more cautious.
Changes are under way, in part because some of the old approaches no longer work and in part because of the demands for tradeoffs earlier in the design cycle.
More complexity, better tools and market pressures are forcing big changes in the PPA equation; rebalancing will become a market differentiator.
Models, hardware-software co-design will take center stage as industry shifts to more re-use to satisfy faster time-to-market demands.
First of three parts: Hardware-software co-design; raising the level of abstraction; pathfinding; finding commonality between designs and increasing re-use; modeling languages.
Second of three parts: Abstractions, re-use, balancing time-to-market with exploration, the role of software, how to build differentiation into designs.
Last of three parts: Faster derivatives; differentiation that matters; standards; multivendor tools vs. single-vendor integration; tradeoffs in stacked die.
First of three parts: The different roles of 2.5D and 3D; progress over the past couple years; 2D vs. stacked approaches; progress on stacked die standards.
Second of three parts: Supply chain changes; testing issues in 2.5D and 3D; what’s missing from the EDA tools arsenal; dealing with an increase in physical effects.
Last of three parts: What tools are needed; stress tests in 3D; hardware-software co-design; who aggregates the stack; risk, responsibility and rewards.
First of three parts: Issues in FPGA prototypes; why it’s becoming more popular; what still needs to be addressed by the EDA industry; choosing the right tool for the job.
Second of three parts: The goal of prototyping; creating a bridge between analog, digital and software engineers to pinpoint problems.
Last of three parts: Measuring the impact of power and software on a design; commercial tools vs. homegrown prototyping systems; the role of prototyping in 3D stacked die designs.
First of three parts: Defining ESL, its uses and its limitations; challenges for keeping models in sync; matching low-level and high-level models.
What’s working and what isn’t at advanced nodes for stacked die configurations.
The move to both fully-depleted SOI and FinFETs may be inevitable over the next couple process nodes, regardless of which one comes first.
Sonics CEO Grant Pierce looks at what needs to change in SoC design, what’s driving those changes, and how all of this will be affected by 2.5D and 3D stacking.
What are the design challenges of the leading GPU company and how are they changing?
Bernard Murphy digs down into what’s changing in semiconductor design and how 3D stacking will affect it.
A look at the next big thing in semiconductors and technology and what it’s going to take to get there.
Open-Silicon’s CEO talks about priorities in business and technology, and how to bring them together.
eSilicon’s CEO sounds off on changes in the supply chain, the skills needed to design a chip at 28nm and the promise of stacked die.
A view from the top at Mentor Graphics into how technology, business and system-level design are changing.
A look at how the growing challenge in verifying complex SoCs and why it’s getting tougher to solve this problem.