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ESL: The Power Savior?

Recently, power has been on the front burner for most design teams. In fact, nearly every corporate executive welcomes a discussion on power solutions given the strong correlation between low-power design and their income statement. So, here’s the question: Is ESL the savior to our power optimization challenge? Well, yes and no.

 

Much of the historical progress in ESL can be attributed to need for system timing analysis. In an RTL-dominant world, timing often brings to mind terminology such as “timing closure” and “setup and hold parameters.” But in the world of ESL, timing concerns involve systemic characteristics such as throughput, bottlenecks and latency. Of course, ESL also has an important role in software development where timing may not even be required.

 

But getting back to the topic of power optimization, recent progress in the ESL domain has enabled system-level designers to analyze power characteristics in the context of software and architectural hardware tradeoffs. Arguably (and based on my last blog entry I anticipate some argument) ESL has always been able to support power analysis.

 

Applying ESL power analysis simply (or not so simply) requires some power modeling effort. In fact, accurate power modeling at the transaction level is quite a difficult task. Fortunately, solutions exist today that not only automate much of the TLM (transaction level modeling) power modeling task, but do so while retaining accuracy close to gate-level analysis results.

 

So if ESL methodologies combined with TLM power modeling solutions enable system level power analysis, why isn’t ESL our savior for low-power design? After all, design teams have more knobs to tweak during the architectural design phase, and the number of knobs quickly reduce to a precious few as the design progresses through the various phases of implementation.

 

The answer is that power optimization is required at every stage of the design process. For instance, system design teams using ESL can optimize HW/SW tradeoffs, processor choices, memory and cache layering, bus parameterization, and test power domains and voltage/frequency scaling strategies, but additional mechanisms such as clock gating, power gating, place & route optimizations, including clock tree synthesis, can only be tuned as design implementation progresses into RTL, gates, and physical representations. In short, Power Optimization requires design team attention and tools at every level of design abstraction.

 

But, there’s good news in all of this. Specifically, ESL power analysis and modeling enables huge opportunities to improve power characteristics. Considering recent advances in TLM power modeling—this is a major step forward. In fact, my customers tell me that Power is one of the key driving forces behind their active investment ESL methodologies. While ESL power analysis might not be the savior, it is most certainly a very key weapon in the arsenal to address the increasing power optimization challenges.

 

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