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Posts Tagged ‘ESL’

ESL: The Power Savior?

Wednesday, December 17th, 2008

Recently, power has been on the front burner for most design teams. In fact, nearly every corporate executive welcomes a discussion on power solutions given the strong correlation between low-power design and their income statement. So, here’s the question: Is ESL the savior to our power optimization challenge? Well, yes and no.


Much of the historical progress in ESL can be attributed to need for system timing analysis. In an RTL-dominant world, timing often brings to mind terminology such as “timing closure” and “setup and hold parameters.” But in the world of ESL, timing concerns involve systemic characteristics such as throughput, bottlenecks and latency. Of course, ESL also has an important role in software development where timing may not even be required.


But getting back to the topic of power optimization, recent progress in the ESL domain has enabled system-level designers to analyze power characteristics in the context of software and architectural hardware tradeoffs. Arguably (and based on my last blog entry I anticipate some argument) ESL has always been able to support power analysis.


Applying ESL power analysis simply (or not so simply) requires some power modeling effort. In fact, accurate power modeling at the transaction level is quite a difficult task. Fortunately, solutions exist today that not only automate much of the TLM (transaction level modeling) power modeling task, but do so while retaining accuracy close to gate-level analysis results.


So if ESL methodologies combined with TLM power modeling solutions enable system level power analysis, why isn’t ESL our savior for low-power design? After all, design teams have more knobs to tweak during the architectural design phase, and the number of knobs quickly reduce to a precious few as the design progresses through the various phases of implementation.


The answer is that power optimization is required at every stage of the design process. For instance, system design teams using ESL can optimize HW/SW tradeoffs, processor choices, memory and cache layering, bus parameterization, and test power domains and voltage/frequency scaling strategies, but additional mechanisms such as clock gating, power gating, place & route optimizations, including clock tree synthesis, can only be tuned as design implementation progresses into RTL, gates, and physical representations. In short, Power Optimization requires design team attention and tools at every level of design abstraction.


But, there’s good news in all of this. Specifically, ESL power analysis and modeling enables huge opportunities to improve power characteristics. Considering recent advances in TLM power modeling—this is a major step forward. In fact, my customers tell me that Power is one of the key driving forces behind their active investment ESL methodologies. While ESL power analysis might not be the savior, it is most certainly a very key weapon in the arsenal to address the increasing power optimization challenges.


Keeping the “E” in ESL

Thursday, October 23rd, 2008

I was in Boston last week and I met with a few customers who shared information about their activities around ESL.  I’m always pleased to meet with customers who are already down the path of ESL. However, I’m often surprised to hear what constitutes ESL for them. In this case, the customer was creating very high level, conceptual models of a system, also known as model based design, to represent a wide range of engineering disciplines across the system (HW, SW, Thermal, Optical). I noted that the models had no representation of actual hardware, just functions in concept which may or may not ever be in actual hardware.

The next night, I was in Philadelphia, at a renowned cheesesteak sub shop, where I watched the Phillies clobber the Dodgers, all the while raising my cholesterol with a great sub. Earlier in the day, I met with another customer who said they were interested in applying ESL and were planning to start by creating UML models. In less than 24 hours, I had met with two customers with completely different concepts of ESL.  Interestingly, neither concept–the model-based design or the UML modeling activity–really fit within my definition of ESL. Specifically, both methodologies neglected the “E” in ESL.  The E in ESL implies electronic hardware and some representation of that implementation. 

While ESL is certainly a design representation above RTL, that doesn’t mean it encompasses every abstraction above RTL. ESL starts and stops within the abstraction of TLM (transaction level modeling), which includes some representation of hardware architecture.  While there are certainly benefits and good reasons to also do conceptual modeling, above ESL, lumping those methodologies into the  ESL bucket dilutes the space and risks confusion in the market.   ESL is a major step in hardware design methodology above RTL and a logical progression in hardware design methodology.  Given the long history of ESL, as we watch it come of age, it seems like a good idea to maintain clarity as to what is and is not within this design methodology.