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Implementing a High Availability ENOVIA Synchronicity DesignSync Data Manager Solution

The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.

Tackling Verification Challenges with Interconnect Validation Tool

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…

Advanced ARM CoreLink System IP Components

Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).

Using Power Aware IBIS v5.0 Behavioral IO Models To Simulate Simultaneous Switching Noise

A new method for dramatically reducing CPU and RAM resource requirements.

Solutions For Mixed-Signal SoC Verification

New techniques that are making advanced SoC verification possible.

Blocking Vs. Non-Blocking

The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.

Mixed-Signal Technology Summit Proceedings

A trove of technical videos and presentations from Cadence and other companies.

TLM-Driven Design And Verification—Time For A Methodology Shift

RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.

On-Chip Communications Survey Results

This report covers the results of an independent, blind worldwide survey covering on-chip communications networks (OCCN), defined as is the entire interconnect fabric for SoCs.

An Analysis Of Blocking Vs. Non-Blocking Flow Control In On-Chip Networks

A look at ways to minimize latency of priority traffic and jitter compared with a single-threaded tag-based protocol approach.


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