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White Papers Archive

Tackling Verification Challenges with Interconnect Validation Tool

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…

Advanced ARM CoreLink System IP Components

Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).

Implementing a High Availability ENOVIA Synchronicity DesignSync Data Manager Solution

The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.

Yikes! Why Is My SystemVerilog Testbench So Slooooow?

When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.

Using Power Aware IBIS v5.0 Behavioral IO Models To Simulate Simultaneous Switching Noise

A new method for dramatically reducing CPU and RAM resource requirements.

Solutions For Mixed-Signal SoC Verification

New techniques that are making advanced SoC verification possible.

Blocking Vs. Non-Blocking

The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.

Mixed-Signal Technology Summit Proceedings

A trove of technical videos and presentations from Cadence and other companies.

TLM-Driven Design And Verification—Time For A Methodology Shift

RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.

Taming The Challenges Of 20nm Custom/Analog Design

A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.