Apple’s new iPad is an interesting device not so much because of what it offers to consumers—that’s certainly interesting in its own right—but because of how Apple built the device and why.

Apple has been scouring the market for seasoned semiconductor engineers of late. The process started two years ago when the company hired a team of former engineers from the late Digital Equipment Corp. who migrated first to PA-Semi, aka Palo Alto Semiconductor, and more recently to Apple. This is a rather odd trend, on the face of it, considering most companies have been outsourcing that part of their computer engineering. Apple had abandoned its own chip development efforts in its Mac line because Intel was beating the pants off everyone (which helps explain why Intel has run into so much scrutiny from regulatory agencies).

The folks at Apple haven’t gone entirely mad, however. The first details of its plan to develop its own chip began leaking out when a deal with a large Asian semiconductor company went sour. According to several sources, Apple’s initial iPhone deal called for this Asian company to provide the logic, memory and processor for the iPhone. But after a year of growing iPhone sales, this company also began shipping its own version of a smart phone that had some of the same feature sets as the iPhone.

Word on the street was Apple wasn’t happy. We have no idea what got broken or smashed in this fit of rage, but realize these folks are still reeling from the lawsuit with Microsoft that claimed theft of Apple’s graphical user interface in Windows 3.0. It doesn’t matter that Xerox invented this technology first. Apple brought it to market first, and it put Apple and Silicon Valley on the map. What took much longer was for Apple to establish itself as a brand that cut across business and consumer markets, which is where the iPhone came in.

Rather than risk a repeat performance with Microsoft, Apple began taking its chip development in-house again. It has been competing for engineers with well-known chipmakers in Silicon Valley, and it has been building in the kinds of things that it has been slammed for in the past, like lower power consumption and better utilization of cores.

But will competitive paranoia really drive a re-aggregation trend, or is Apple just so unusual that it will continue to carve its own path? These kinds of trends are best viewed in retrospect, and right now it’s still something happening in the future. The iPad isn’t on shelves yet and so far Apple is still using Intel chips in its Macs.

–Ed Sperling

For all intents and purposes, the downturn appears to be over. Like the California drought, it takes time to refill the reservoirs, but at least the economic base level is rising.

All of the leading indicators in the semiconductor market point upward and to the right. iSuppli reports that distributor inventories are below average, which is particularly interesting given that the electronics content of devices has been increasing steadily. It’s cheaper, after all, to design in an electronic component than to build a mechanical one, something that should become even more obvious once the automobile market begins rebounding.

That’s also evident in iSuppi’s prediction for the semiconductor equipment sector, which it expects to grow about 47% in 2010. Given the steady rise in foundry capacity utilization, that’s a strong indication of how the market is expected to play out over the next couple of years.

Overall market projections for growth on a global base seem to support this. The Economist’s economic indicators show all major economies are poised for GDP growth in 2010, with China leading the pack at 8.6% and the United States following at 2.8%. Both Europe and Japan will show slight growth, but at least it will be in positive territory. Equally important, inflation is predicted to stay well behind those numbers, as well, leading to a net positive growth across most of the world’s economic engines.

The big sticking point remains jobs. For highly skilled engineers jobs are still available, although in some cases actually taking a job may require relocation. In the case of a low-power engineer, that relocation may be to a place like Japan or Europe. In the case of an RTL engineer, it may be India or China. The recovery so far seems to have left many others stranded, waiting for companies to become comfortable enough with growth projections to begin the hiring process again.

The good news is that by this time next year it’s unlikely we’ll have time to reflect on just how nasty a global downturn can be. And that will be a very good thing, indeed.

–Ed Sperling

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year.

GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and UMC to semiconductor companies like IBM, STMicroelectronics and Samsung to EDA providers like Synopsys and Cadence.

Virtually anyone can become a member of the GSA, and given the list of members it appears that a good portion of the industry has signed on. But you have to get elected to the board of directors, which basically puts you into the center of the customer and supplier ecosystem. The proof is in the attendance numbers. Average attendance at board meetings of non-profit organizations is roughly 50%. The GSA’s attendance is closer to 100%, according to GSA president Jodi Shelton.

For two board seats in two categories there are 13 different executives in the running from as many companies. One is for the broadly defined semiconductor board seat, where 10 different companies are competing. The second is a new category of value chain producers (VCPs), where eSilicon, Global Unichip, and Silicon 360 are each vying for the spot.

While most of this happens behind the scenes—the lobbying for votes with recorded messages and the campaigning to members—what’s interesting is the hidden message behind all of this. The GSA is representative of the industry, and increasingly no company can stand on its own. An SoC isn’t the work of a single company—even at big companies like Intel, IBM or Samsung—which means it’s now increasingly important to be at the center of the ecosystem to remain competitive.

That makes the stakes higher than ever before, and it means GSA elections should become even more hotly contested at every process node—most likely with new spinouts like the VCP definition. And like all complex designs these days, this should get very interesting.

–Ed Sperling

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs.

It also has been revised on more than one occasion as the time frame in which the number of transistors doubles has floated between 18 and 24 months. And it has been predicted to die on multiple occasions, starting back at 1 micron (aka 1,000nm) when lithography was believed to be at its physical limit.

Moore’s Law has defied all predictions and all odds. Some companies have jumped off the bandwagon and moved in different directions, while the largest continue to adhere to its advancement with almost religious fervor. But the real future of Moore’s Law be less of a mark of size of the company making the investment in a new chip than a piece of an overall system that limits the use of advanced process nodes for extremely regular structures in places where space matters but little else.

As we move into 3D stacking over the next few years and tighter integration between software and system design, the real future of Moore’s Law may be less impact on the overall system and less importance for what makes one chip different from another. Rather than come to an abrupt end, Moore’s Law may be the part of the chip that is most commoditized rather than the part that wields the competitive edge.

This is a rather shocking end game for a formula that has dictated how chips were developed throughout most of the history of ICs. But it also means that companies will need to start looking beyond Moore’s Law and replacing it with new formulas, approaches and structures—ones that may have far less impact over the long haul but which will be just as important for the generation of semiconductors that benefit from them. The same variables of area, power and performance still matter, but they will no longer be defined by the line width between all the components on a chip.

–Ed Sperling

The pace of change in system-level design is no longer confined just to technology. It now hinges largely on whether enough engineers can make the leap from RTL or synthesis or verification or any other specialty to systems engineer.

This is no small feat. It requires re-tooling and learning of modeling and other concepts that until now have been largely at the architectural level. It may even require an understanding of software. But the biggest hurdle may be getting engineers to recognize that modeling and high-level synthesis actually work and can save them extraordinary amounts of time.

While TLM 2.0 may be fine in theory, the application hasn’t been essential for most engineers working on SoCs even at 65nm. At 45nm and beyond, power islands are becoming a reality and so is the integration of complex blocks and clusters of blocks. Some of this stuff simply can’t be done by hand—at least not in the market window available to engineering teams. There are too many gates, too many possible interactions, and way, way too much complexity for verification.

While that doesn’t preclude engineers from continuing to use spreadsheets, it does limit what they can accomplish on those spreadsheets and how quickly. And while it doesn’t mean designing testbenches in analog blocks will change, how those blocks get integrated will change. And perhaps more important, the complexity of software and the inclusion of software engineers in this whole process now means that engineering managers cannot afford to keep them idle until chips are fully designed and taped out.

For the first time in memory, the pace of change is not being limited by the technology available to engineers. It is being limited by the ability of the engineers to comprehend the changes, ramp up their skills, and cross into new areas that were previously the domain of different experts. At future nodes, those walls need to be defined and then redefined, and it’s up to engineers to figure out where they want to fit in the new order.

–Ed Sperling

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their revenue going into the downturn.

There are five very good reasons for this:

1. The downturn has shown many companies they need to be hedged across multiple markets if they want to continue showing growth in future years. Because of the convoluted supply chain, which is spread across continents and across different design cycles, not all parts of the design chain feel the pinch at the same time. As a result, we’re seeing moves into a variety of areas such as Mentor pushing into Android devices and Synopsys moving into software prototyping.
2. Not all parts of the industry are poised for significant growth in the future. There will jam-up of competitors in some areas because there are far fewer design starts. While the design starts that do happen will be bigger and more complex, there will be fewer companies developing them because of the cost. In addition, there will be less creativity in other areas that were consistent revenue sources because rising complexity coupled with a lag in lithography technology is forcing more restrictive rules on designers. Just to get chips out the door at 32nm and beyond will require more regular shapes and layouts, which doesn’t bode well for a slew of players fighting for a shrinking place and route market.
3. The value has shifted from just hardware or software to hardware and software. Co-verification, software modeling and prototyping and even operating system and some application development is being done by chipmakers. Companies that can bridge these two worlds effectively will reap bigger rewards than those doing the same thing they were doing two years ago.
4. The pain points are getting more granular. While SoC design is moving to a higher level of abstraction, verification has more things to test. The models work great for blocks, but now those blocks have to be tested, as well. And they have to be integrated and share resources, particularly in multicore chips. Add in various power modes and power islands and complexity goes straight up and off the charts. That also has created new opportunities for startups to gain entry into the industry, and the big guys are struggling to either absorb them or compete against them.
5. There is growth in tangential markets, and far better security in reaching beyond the classic EDA world. Mentor’s push into DFM and test, mechanical analysis and wiring harnesses is a case in point. Synopsys’ push into IP and high-level synthesis are well beyond its normal flow. Even Magma has pushed into analog and mixed signal place and route.

As we emerge from this downturn—and we are still not fully emerged—these moves are likely to become even more pronounced. What is uncertain is just how the industry will look when these changes take root.

–Ed Sperling

For all the talk of restricted design and increasing complexity, it seems that what’s really happening is that restrictions are being lifted off one group and placed on another.

This happens from time to time in system-level design, usually at an inflection point in the overall system development process or at the start of a new process node. For the past couple decades, much of the creativity in semiconductor development was done at the design engineer level, often but not always in conjunction with the chip architect, while most of the heavy lifting and saving the day was done at the back end in verification and in manufacturing.

At 32nm and beyond, it’s the design engineers who are losing some freedom to say how things can be placed on a chip, what can be done to fix design flaws after the fact and what new approaches can be added. Architects now have more control over the whole SoC than ever before—and there are plenty of people who will argue the pros and cons of that for years to come—and the foundries are staking a claim from the back-end to make sure that what’s designed can be manufactured. Nobody makes money if there are yield problems or if a chip is late to market.

What’s driving this shift are too many variables on the front end and too much data on the back end. Architects have to wrestle with power budgets, power islands, business issues and marketing priorities. Foundries have to deal with massive amounts of data that get even bigger with computational scaling, and verification and debugging still have to deal with all of these issues. Costs are rising, respins can force companies to lose market windows, and complexity is forcing some choices that didn’t have to be made a couple process nodes ago. And in the midst of all of this, companies are now responsible for developing larger and larger portions of the software stack.

In between are the engineers who work at various phases of the flow, from design to layout to verification, watching what appears to be a massive shift in their market on all sides. They’re correct in sensing the changes. These are significant, and it’s too early to tell which jobs will ultimately rule the roost or at which process nodes. But whatever changes occur, you can be certain they won’t be the last.

—Ed Sperling

There’s more to the Intel-AMD settlement than meets the eye.

While Intel will be paying out $1.2 billion to AMD as part of the settlement—and that’s a large chunk of money in anyone’s book—it’s a relatively small price to pay when it’s amortized over 10 years and can open the door to even bigger markets for Intel. And that’s just what this is, a down payment on the future.

Intel has been smacked by the EU ostensibly over the AMD suit. It also has been threatened by regulators in the U.S., Korea and Japan for its business tactics in the PC business. But the PC business isn’t growing by leaps and bounds anymore, and if Intel were to continue fighting in the PC world it would be endlessly sidetracked from more lucrative battles with its Atom processor and potentially its semi-custom SoC business.

Intel’s chief competitor in the Atom world is ARM. Going into battle against ARM with regulators clamping down on its business practices with its x86 processors isn’t a good thing. This doesn’t mean Intel won’t play to win in those markets. But it’s a lot easier to go after new markets without the label of a monopoly.

Intel needs AMD, if for no other reason than to act as a shield while Intel attempts to gobble up market share in the netbook and smart phone world. And it needs to be seen as just one more player in a competitive market to go after the big SoC makers. The company has almost $13 billion in cash, and these days it’s one of the very few bright spots in the semiconductor world. It has the largest R&D budget in semiconductors, its own fabs and an incredibly aggressive road map that even few ecosystems can sustain. And perhaps even more important, the company has a relentless focus on efficiency and growth that has always been part of the corporate culture.

If this were a game of chess, Intel’s payment to AMD would be like sacrificing a rook to take the opponent’s queen. And after that, it’s just a matter of gobbling up all the other pieces and keeping the king harmlessly out of trouble.

–Ed Sperling

The big companies felt the pain first, or at least they acknowledged it. In big companies, pain is felt in dollars. In smaller companies, it’s felt everywhere because every person counts.

What the big IDMs did first was offload their fabs, or at least open them up for enough business to sustain their investments in new technology. That’s the strategy taken by IBM, and it appears to be the same at Intel and Toshiba. It was simply too expensive to do it alone.

Those who couldn’t sustain a fab, with the massive investment in equipment and process technology for each new node, became fabless. And many companies that started out fabless because there was no need to own a fab either thrived because they were in the right markets—think Broadcom, Qualcomm and a handful of others—or they struggled to raise their visibility because they didn’t own fabs and didn’t have that kind of direct communication.

Things are changing again. Outsourcing is on the rise, new business models are emerging and technology that was once considered an interim step—think FPGAs and off-the-shelf IP—has now gotten to the point where it’s sometimes as good if not better than what companies can create themselves, particularly with their ever-shrinking payrolls.

The interesting part of all this is that coming out of a downturn companies are more open to trying new things that can add efficiency or improve their final product. Downturns bring plenty of pain, both before and after, but they also bring some interesting changes that tend to stick around for quite awhile.

-Ed Sperling