What does the economic bailout have to do with system-level design? Probably more than you’d guess.

Convergence of the front and back end of chip design, combining everything from software with verification planning at the architectural level, is now being converged with one other element—business. And that business element is reaching far deeper than ever before.

Business has always had a big role in designing systems, of course. Cost is a big factor in designing chips that can run tens of millions of dollars and threaten the solvency of even big companies, which is why there is such a huge focus on verification these days. It’s also a huge factor in manufacturing the chips, which is why even the most stalwart IDMs (Intel included) use foundries for some of their production.

What’s changed is that the complexity of designing chips—both time and money—are forcing more companies to work with partners. That means the weakest link in the chain is the weakest partner.  Until a few weeks ago, that was viewed primarily as a technology or engineering issue. It’s now a liquidity issue, and it reaches beyond your partners to their partners and into everyone’s combined customer base.

Credit crunches can significantly raise the cost of doing business. They make borrowing money more expensive. That, in turn, can make end markets look less attractive, completely change the ROI model, and they can bring some of the best-run companies to a standstill.  Analysts’ projected softness in the consumer electronics market knocked 18 percent off Apple’s stock on Monday. But the real question, which so far hasn’t been answered, is what that will do to new design starts in Apple’s core market—and how that will ripple across the industry into other areas.

That helps explain some of the side comments at the Common Platform conference this week. Business concerns are giving everyone in the design chain neck strain. They’re looking back to see whether their business partners are all aligned, and they’re looking forward to see if there will be enough demand to warrant a massive investment. And they’re dropping one-liners about what they’ll be doing in five years—or maybe three weeks, depending on what happens on Wall Street.

There must have been a half-dozen such mentions in a two-hour span. The news is rampant. The market is down 777 points one day, back up 485 points the next. These are the kinds of swings that make the entire system look unstable, and they get people thinking about whether to invest in a new chip or whether to use some caution or whether to slam on the brakes and move a half-node instead of a full node, or no node at all.

There have been numerous credit crunches in U.S. history. The only one that proved calamitous was in 1930. Some were politically motivated—witness the battle a century earlier between President Andrew Jackson and the central bank. Others were caused by bubbles gone bust following run-ups in the stock market. J.P. Morgan was famous for averting market collapses by pumping up the cash in banks.

But no matter whether the current fiscal crisis is resolved quickly, or whether it continues to rear its head, the effects this time will be different. Design cycles are no longer insulated from the overall business climate, and the business climate right now is extremely volatile.

What do you think?

Gordon Moore should be proud. At every process node, the number of transistors goes up, but so do the number of engineers you need to develop a chip.

This may not be immediately obvious to anyone who’s actually working on a new chip. You’re probably part of a team that uses fewer engineers than several years ago, purchasing off-the-shelf IP blocks, and leaning heavily on design automation tools to make sense of this unbelievably complex project. But when you consider just how difficult it’s getting to create a new chip—multiple power domains, timing that is complicated by multiple cores and shared busses, more and more functionality, low-power requirements, verification and debugging—and how many people are working to make the pieces work together across these new flows, that’s more engineers than anyone would have dreamed of when Moore’s Law was first put to paper in 1965. Lots more.

In fact, when you really dig down into Moore’s Law, this economic formula isn’t quite so simple and clear-cut as it sounds. On paper, the number of transistors does double every couple years, more or less. That number and formula has been rewritten several times since it was first introduced, but the general scenario is the same whether it’s every 18 months or 24 months. What isn’t so clear is exactly who is realizing the savings.

Yes, it does cost less to manufacture a wafer with reduced line widths, if the yield is high enough. But that’s a big if. Defect density is higher at every process node, which is something most foundries and IDMs don’t like to talk about. A defect at 130nm may go unnoticed if it doesn’t interfere with a chip’s performance. That same defect at 65nm may have a completely different impact, and at 32nm it may wipe out multiple chips. That costs money.

Tools also are more complex than they were in the past. Standards like TLM 2.0 do make it possible to re-use functional, power and timing models, but you have to create those models in the first place. It requires a persistent level of training and retooling for engineers to make that happen, and that takes even more money.

Nowhere is that more evident than in multicore chips. It can be argued that Moore’s Law really ended after 90nm, because technically multiple cores are multiple chips on a single piece of silicon. This is an argument you probably don’t want to get into, though. It’s like taking a definitive position on whether yeast is alive. Yes, it produces alcohol, but what else does it do? After 90nm classical scaling ended, chips ran too hot, and the only way to solve the problem was to combine multiple chips and lower the clock speed. Is that one chip? Well, maybe.

One thing we know for certain, though. It’s a nightmare to write code that can scale on multiple processors. It takes a lot of software engineers a lot of time to do the same thing one engineer could do on a single core. And that costs even more money.

No one has ever done a full analysis of the costs behind Moore’s Law, but the numbers certainly aren’t as clean as the proponents of this equation would have you believe. As the front and back ends of chip development continue to merge with things like restrictive design rules and design for manufacturing, it may be high time someone really looked at the total economic picture.

What do you think?