The EDA world is either doing better than most segments of the economy or coming apart at the seams, depending upon your perspective and your definition of exactly what an EDA company is. But at least one trend seems clear: As we push into the world of system-level design from chip design and SoCs instead of ASICs, the high-level trend is broader companies with more complete integrated packages rather than lots of little pieces.

While this may cause all sorts of gyrations and lots of discomfort in the interim, the industry around system-level design tools ultimately will emerge significantly stronger if not overtly different. It has no choice. Either it begins eliminating pain for engineers developing incredibly complex chips or they’ll lose market share to companies like IBM and Toshiba, which already have their own proprietary tools, and the foundries, which easily could cobble together a suite of tools on their own.

To no small extent, Mentor Graphics and Synopsys are well along the path of creating much more integrated flows that reach well beyond the bounds of where they used to be. Cadence clearly sees the need to change, as well, which accounts for the board’s recent actions to boot all upper management—including longtime CTO Ted Vucurevich this week. He mysteriously has disappeared from the management roster, even though the company never announced his departure.

Cadence’s new CEO, Lip-Bu Tan, has more experience on the finance side than anyone since former CEO Ray Bingham, but he also has one other benefit. According to company insiders, he has very strong ties inside China, which Cadence’s board clearly sees as a growth opportunity.

Magma, meanwhile, has gone under a cloak of secrecy in recent months to develop its new strategy. Sources say the company is working on automating parts of the analog flow, but exactly what and how successful Magma will be in that space remains to be seen.

What happens to a number of startups along the way is another question. Our guess is that consolidation will begin in earnest when the economy hits bottom and begins climbing back from the depths of despair. The bigger question is where do the next startups get going. Silicon Valley will still be strong, but not all the VC money will end up there.

What do you think will happen next?

The easy stuff is over, not that anything was ever really easy in the semiconductor world. But getting the most from a chip in terms of lowering power and boosting performance will no longer be a function of the silicon alone.

Most software engineering has been done with existing languages and operating systems, but the well-known versions are aimed at general-purpose computing. They’re grossly inefficient for most tasks, and most of them are based on the need for regular communication between various components.

In the future, application code—not the operating system—will have to be written directly to the chip. That can be done in Verilog or some other language—with a superset of limited functionality built on top of that rather than underneath it. This is something along the lines of what Intel has started thinking about with its multicore development language, but even that relies heavily on hardware services that span a device and backward compatibility. The real gains in performance for the least amount of power will come from direct interaction with one or more cores for a very specific purpose.

Many engineers who developed chips for the military decades ago are familiar with this kind of hardware-software interaction, but it’s been largely absent from the industry because classical scaling on CMOS has made it possible to gain performance at every process node. That ended at 90nm, and short of a couple tricks such as moving from CMOS to SOI, straining silicon and adding more cores, the Moore’s Law roadmap will run out of steam. It still will be technologically possible to advance to future nodes, but the benefits in performance and lower power will disappear.

Radically changing software design could add a couple more nodes to the road map, as well as improve the performance and lower the power requirements of older process nodes. But it also will require significantly more complex modeling of the interactions of the software and the hardware rather than just making sure the software works with the hardware. Compatibility is only part of the problem. Efficiency in communication between hardware and software is the other piece, and that has never been fully developed.

In the ESL world, we will always live in interesting times. What remains to be seen is just how much of a curse this actually becomes.

“Just because it’s difficult to do doesn’t mean it’s a differentiator.”

That succinct and rather meaty statement belongs to Aart de Geus at Synopsys, but most executives in the chip world have been spouting these kinds of revelations for months. There’s a fundamental shift underway, which is evolving from focusing on a single chip to seeing that chip as part of a system. The final product has become so complex that no single engineer can understand every facet of the development process with the same level of detail as in the past.

To many engineers, this is a career-changing concept. Understanding the underpinnings of chip design and development was considered invaluable, and the biggest rewards went to those who understood it best. That was then. This is now. Getting the job done quickly, with fewer people and fewer re-spins is paramount.

In many respects, tools like TLM 2.0 and IP-XACT work like a black box.  You don’t need to know all the details to make it work, which means an engineer with less training actually can do as much or more than someone mired in the old way of doing things. And clunky internally developed tools often are more of a hindrance than a help, even though the thinking among many managers is that they’ve already paid to develop the tools and therefore they’re free. They’re not. Inefficiency costs time and money.

And if this sounds like a huge change in the digital world, wait until it starts hitting the analog world. The economics of one-off designs, not to mention the time it takes to create them, are putting pressure on chip developers to adopt more standardized approaches. Digital was first, and even that hasn’t been an easy transition. Pushing from digital chips to complete systems, including application software, is still a huge challenge.

In the analog world, the whole design process has been stuck in the same place it’s been for the past several decades. The rule of thumb is that it takes 10 years to create a good analog engineer and it takes years to create a good analog design. As analog and digital find their way into the same system-level design process, no one can wait that long anymore. They have to work at the same process node—something most analog engineers will cringe at—and they have to be developed concurrently.

Automating development could shorten that time dramatically, but it will require wholesale changes in the ranks of established companies that have built a reputation on developing processes that age far more slowly than in the digital world. In the end, defining what is the best way of doing things is a business decision, not a scientific one—as painful as that realization may be.

If customers aren’t willing to pay for EDA or ESL tools, then something is clearly missing from the equation. It’s not that there isn’t value in the tools. Clearly, you can’t get the job of creating a system on chip done without them. But the real value has shifted.

These shifts have occurred at various points throughout the history of semiconductors. The big question is whether they’re going to happen more frequently now that the industry is global, chip development is more complicated and market windows are shrinking.

Smaller shifts tend to play into the hands of smaller companies. They can create tools more quickly to deal with new challenges in development, but they don’t have the mass to guarantee continuity. Bigger and more frequent shifts leave customers running for cover of safety, which in the chip industry is roughly the equivalent of investors buying U.S. Savings Bonds even though the interest is low.

It’s impossible to tell when you’re in the middle of a shift which way the wind is blowing, but the longer the recession lasts and the harder it is to get to 22nm production, the more likely that the big guys will begin buying more pieces to cement their place in history. While all we heard about in the year 2001 was disintermediation—basically splitting apart big companies into their viable components—the current downturn may push things entirely the other way.

What do you think? Are we headed for consolidation? And if so, what does the new consolidated company look like?