The economics of engineering chips are changing again.

We’ve been hearing for several process nodes about runaway non-recurring engineering costs and the rising costs of masks and how Moore’s Law would meet an abrupt end because no one could afford to stay the course. And while it’s true that not everyone did stay the course, the solution has turned out less onerous than many predicted because of derivative chips, skipping nodes and better design for manufacturability tools.

Those are business decisions, of course, and the convergence of business and technology at the leading edge of design has been obvious since 130nm. In fact, business decisions are now as creative and well-thought-out as many technology advances. Restrictive design rules are largely business decisions, too, although this time dictated by the foundries, while high k/metal gate technology is a technology that enables many of those business decisions.

Modeling of hardware and power is both. It solves many technology problems by raising the level of abstraction, but it also requires a leap of faith from the technology and the business—arguably the first such technology to ever do that. In the past, either the chip design side of the house or the business folks needed to see concrete results before they invested time or money—or both. In this case, they both have to buy into the concept, and that’s something of a quiet revolution in chip design.

But modeling does have one great advantage—the alternative is uglier than taking a big gulp and hoping for the best. Adding more re-spins, boosting NRE costs and ultimately missing market windows are unthinkable, and with complex SoCs at the leading edge of design, that may be the alternative.

–Ed Sperling

In the end, it all comes down to money. In the beginning it’s all about money, too. But when it gets into the middle of the cycle, people seem to forget about that.

System-level design, Moore’s Law, abstract modeling, lithographic advances and everything in between have all been caught in the worst downturn since the great depression. The problem is that instead of just independent sectors being slammed, the entire world went down together. Jobs got cut, foundry orders dried up, consumer demand withered and commercial demand for computers and communications infrastructure—the old standby’s of semiconductor development—stalled.

Put in perspective, semiconductor design weathered the storm rather well. The EDA market was down for the first time in its history, and people will be speculating on why that happened for years to come. Design engineers were cut. Budgets were cut, and end customers weren’t buying as many tools as in the past.

Moreover, the whole picture didn’t make sense to people because from a portfolio management approach, you’re supposed to have a stable portfolio when you reach about 20 different investments. That could be different market sectors and different countries, or different tools that play across those various sectors and geographies.

While modeling makes sense at 32nm, most companies have been sitting back a couple nodes waiting for the market to begin showing life again. The recession that began in December 2007 has been long and deep, and most people have been struggling just to get through it.

As of the past quarter, it appears the downturn is either over or nearing the end. Foundries are investing in new process technology, orders for EDA tools are up, and Asia is rebounding faster than anyone predicted. In other markets, home sales are up, consumer confidence is up, and so are all the major stock indices. Some companies are even hiring again.

And finally, with money beginning to filter into the design world, we’ll be able to actually start exploring all the new techniques and challenges that everyone has been talking about since before the recession began—and actually solve some of the thorniest problems electronics design has ever witnessed.

–Ed Sperling