Verify, Verify, Verify
Verification has claimed the biggest chunk of design time and cost for many generations of chips, but it has now been elevated from design headache to the poster child of what’s ailing semiconductor design.
The question being asked in many quarters, and also in many different ways, isn’t whether the verification approach and tools are right. It’s whether the fundamentals of design and building chips need to be re-thought from the ground up.
Unfathomable complexity, fear of failure and lack of understanding about new tools and models has led many engineers to question whether the industry needs to slow down the push from one node to the next. If chips cannot be verified on time and within a prescribed budget, then they are unlikely to get produced.
The first evidence of this is node skipping by chipmakers and the introduction of restrictive design rules by foundries. The next step is the introduction of verification IP all the way at the front of the design. What comes next is anyone’s guess. Some of the suggestions include platforms, programmability and entire blocks that can be built almost as a general purpose chip, with much more limited design flexibility.
What is clear is that we are at a tipping point where verification of all pieces of the chip—including application software—are becoming so time-consuming and complicated that something has to change. It may be the tools, it may be the overall approach to design, or it may be a combination of both. But without that, there may be far fewer chips rolling out the door at advanced nodes and what we have seen as progress in chip design for decades will slow dramatically.
–Ed Sperling
October 2nd, 2009 at 1:47 pm
What a somber and gloomy outlook. I agree that verification is a big problem, but there is a lot going on to address the issues. The big problem is inertia. You can’t improve things without changing things.
For example, I see people benchmarking the latest high-level synthesis tools by comparing against existing hand generated RTL. This totally misses the point and many of the advantages that come from the adoption of high-level synthesis (btw – it usually matches or beats). It enables architectural exploration which will find much better design solutions (reported gains just this week range from 15% to 30% area reductions and similar gains in performance, power etc). It starts from a high-level description of the design, on which we can do functional verification much faster, and more effectively. It allows verification to concentrate on the important things first and worry about implementation details later. Debug is faster and the list goes on and on.
Yes – the tools for these are still maturing, but if you want to do the biggest, baddest chips on the block, then you have to go out on the edge. Otherwise stick with what you have and do the best you can. You may muddle through until ESL tools become more mature and it becomes obvious to the world that this is the way to go.