Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs.

It also has been revised on more than one occasion as the time frame in which the number of transistors doubles has floated between 18 and 24 months. And it has been predicted to die on multiple occasions, starting back at 1 micron (aka 1,000nm) when lithography was believed to be at its physical limit.

Moore’s Law has defied all predictions and all odds. Some companies have jumped off the bandwagon and moved in different directions, while the largest continue to adhere to its advancement with almost religious fervor. But the real future of Moore’s Law be less of a mark of size of the company making the investment in a new chip than a piece of an overall system that limits the use of advanced process nodes for extremely regular structures in places where space matters but little else.

As we move into 3D stacking over the next few years and tighter integration between software and system design, the real future of Moore’s Law may be less impact on the overall system and less importance for what makes one chip different from another. Rather than come to an abrupt end, Moore’s Law may be the part of the chip that is most commoditized rather than the part that wields the competitive edge.

This is a rather shocking end game for a formula that has dictated how chips were developed throughout most of the history of ICs. But it also means that companies will need to start looking beyond Moore’s Law and replacing it with new formulas, approaches and structures—ones that may have far less impact over the long haul but which will be just as important for the generation of semiconductors that benefit from them. The same variables of area, power and performance still matter, but they will no longer be defined by the line width between all the components on a chip.

–Ed Sperling

The pace of change in system-level design is no longer confined just to technology. It now hinges largely on whether enough engineers can make the leap from RTL or synthesis or verification or any other specialty to systems engineer.

This is no small feat. It requires re-tooling and learning of modeling and other concepts that until now have been largely at the architectural level. It may even require an understanding of software. But the biggest hurdle may be getting engineers to recognize that modeling and high-level synthesis actually work and can save them extraordinary amounts of time.

While TLM 2.0 may be fine in theory, the application hasn’t been essential for most engineers working on SoCs even at 65nm. At 45nm and beyond, power islands are becoming a reality and so is the integration of complex blocks and clusters of blocks. Some of this stuff simply can’t be done by hand—at least not in the market window available to engineering teams. There are too many gates, too many possible interactions, and way, way too much complexity for verification.

While that doesn’t preclude engineers from continuing to use spreadsheets, it does limit what they can accomplish on those spreadsheets and how quickly. And while it doesn’t mean designing testbenches in analog blocks will change, how those blocks get integrated will change. And perhaps more important, the complexity of software and the inclusion of software engineers in this whole process now means that engineering managers cannot afford to keep them idle until chips are fully designed and taped out.

For the first time in memory, the pace of change is not being limited by the technology available to engineers. It is being limited by the ability of the engineers to comprehend the changes, ramp up their skills, and cross into new areas that were previously the domain of different experts. At future nodes, those walls need to be defined and then redefined, and it’s up to engineers to figure out where they want to fit in the new order.

–Ed Sperling

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their revenue going into the downturn.

There are five very good reasons for this:

1. The downturn has shown many companies they need to be hedged across multiple markets if they want to continue showing growth in future years. Because of the convoluted supply chain, which is spread across continents and across different design cycles, not all parts of the design chain feel the pinch at the same time. As a result, we’re seeing moves into a variety of areas such as Mentor pushing into Android devices and Synopsys moving into software prototyping.
2. Not all parts of the industry are poised for significant growth in the future. There will jam-up of competitors in some areas because there are far fewer design starts. While the design starts that do happen will be bigger and more complex, there will be fewer companies developing them because of the cost. In addition, there will be less creativity in other areas that were consistent revenue sources because rising complexity coupled with a lag in lithography technology is forcing more restrictive rules on designers. Just to get chips out the door at 32nm and beyond will require more regular shapes and layouts, which doesn’t bode well for a slew of players fighting for a shrinking place and route market.
3. The value has shifted from just hardware or software to hardware and software. Co-verification, software modeling and prototyping and even operating system and some application development is being done by chipmakers. Companies that can bridge these two worlds effectively will reap bigger rewards than those doing the same thing they were doing two years ago.
4. The pain points are getting more granular. While SoC design is moving to a higher level of abstraction, verification has more things to test. The models work great for blocks, but now those blocks have to be tested, as well. And they have to be integrated and share resources, particularly in multicore chips. Add in various power modes and power islands and complexity goes straight up and off the charts. That also has created new opportunities for startups to gain entry into the industry, and the big guys are struggling to either absorb them or compete against them.
5. There is growth in tangential markets, and far better security in reaching beyond the classic EDA world. Mentor’s push into DFM and test, mechanical analysis and wiring harnesses is a case in point. Synopsys’ push into IP and high-level synthesis are well beyond its normal flow. Even Magma has pushed into analog and mixed signal place and route.

As we emerge from this downturn—and we are still not fully emerged—these moves are likely to become even more pronounced. What is uncertain is just how the industry will look when these changes take root.

–Ed Sperling