There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump.

Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chips that used to be in a package is a lot different than designing a chip where the logic may be spread across two or more die that are bonded together. And putting memory on top of a processor and calling a 3D chip is not the same as optimizing the chip for performance, power and understanding the thermal implications of putting one block on top of another.

On the flip side, everyone is talking about the same direction. It’s just a question of where they sit on that evolution from system-in-package to a true 3D layout and synthesis. Memory makers are already building 3D configurations, and some of the most advanced chipmakers are already working on 3D chips they’re not willing to talk about just yet.

The next step is to commercialize this process beyond just a few, which is where EDA tools come in. The companies that can bridge the gap between the most advanced digital processes and lagging analog processes stand to profit handsomely because they will be acting as a bridge between the economic necessity of some companies to push forward to the next node and the economic pain that kind of approach is causing other companies.

There is much work to be done in this area, of course. Modeling in 3D doesn’t exist today. Through-silicon vias are still a work in progress. Secondary problems such as electrostatic discharge, electromigration and parasitics need to be dealt with. Thermal issues need to be dealt with at the architectural stage. And standards have to be developed across the board.

But none of these is new. What is new is the prospect of unifying both ends of the semiconductor spectrum in SoCs that can both improve performance and use less power, which can use the manufacturing process that makes sense for a particular technology, and which can re-use vast amounts of previous chips to lower the overall cost of development.

In semiconductor design, 3D stacking is an enormous opportunity. The only question now is who will get there first.

As the design industry plunges into DAC this year, it’s beginning to look like a completely different industry.

It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of the design.

There is more pressure to do more up front than ever before. There also is more pressure for EDA vendors of all sizes to find unique growth markets that extend beyond the latest process node on the Moore’s Law road map. While there will still be some components that have to be made at the latest process node, there will be many others that do not—particularly as new techniques of building chips such as 3D stacking or systems-in-package with much faster interconnects and networking schemes begin rolling out.

This has set off a positioning scramble the likes of which hasn’t been seen since EDA was a nascent market. As large companies begin reaching out in new directions—Cadence with software and IP, Synopsys with software prototyping and Mentor with board-level design—as well as continued expansion by the IP vendors, we’re about to witness some fundamental shifts that can only be characterized as good.

The mantra among many EDA industry executives is that necessity is the mother of invention. There is plenty of necessity, and right now we’re witnessing the invention.

–Ed Sperling

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees.

Look across the entire SoC design chain, however, and the picture looks a lot different. Software is taking up an increasing amount of the NRE. The fact that more software engineers are being hired these days than hardware engineers is a well-known fact. What isn’t known among the hardware engineers is exactly what they do.

They don’t speak the same language. They generally aren’t even in the same age group as hardware engineers. And their verification techniques are completely different than on the hardware side. Perhaps even worse, inside many companies the budgets are split between the two sides rather than united into a single organization, giving each side unrealistic impressions about just how much it really costs to create a design.

While the upper management is fully versed in these kinds of cross-department costs, the lack of regular communication between the hardware and software teams has generated a lot of misinformation. They’re both part of the same process, and the aggregate cost is part of the same budget.

Perhaps even more baffling to both hardware and software groups is the cost of integrating third-party IP, which is becoming increasingly popular as chipmakers seek to cut their time to market. In many cases, that cost is split between both groups because it can have an effect on the performance of both the hardware and the software. Think memory and I/O IP, for example. Both hardware and software need to work with it effectively.

And finally, there are hardware bugs that can be fixed with software and software bugs that can affect the functioning of hardware. And when problems show up, particularly at the last minute, allocating costs may not be as clean as each side of the fence would hope—or as measurable.

The bottom line: The cost of developing chips at each new node is going up. You just have to look for those costs in different places than in the past.

–Ed Sperling