Moore’s Law Revisited
It’s no surprise that Moore’s Law can continue for many more generations. Intel’s road map already extends down to 5nm, most likely with carbon nanotube FETs, tunnel FETs, graphene TSVs and maybe even fully depleted SOI to replace bulk CMOS.
The rest of the industry has been hanging back a node or two, gliding on the coattails of what Intel and companies like IBM, Samsung and STMicroelecronics develop—when processes are more stable and tools are available to automate this complexity. That’s still the current strategy of big fabless companies such as Broadcom and Qualcom, and even giants such as Apple.
But even the big guys are starting to encounter problems. It’s not that Moore’s Law can’t continue, but except for Intel and maybe IBM/Samsung it probably won’t. STMicroelectronics is considering selling off its digital division. lIBM and Samsung have joined forces in research. And most of the rest of the deep research is now being done by universities, although not necessarily for the same purpose. And that’s only part of the equation. The cost of a fab at 5nm is probably beyond even Intel’s capabilities. And it’s likely that giant foundries such as GlobalFoundries and TSMC won’t see the volume for many years to warrant equipment purchases that could run tens of billions of dollars.
This hardly means the end of the semiconductor business as we know it. But when you come to a T in the road, you typically turn left or right. The strategy in the past has been to extend the road forward, but the cost of development is getting too high. There is no wall. But engineering the road beyond 10nm is extremely costly.
Even the followers along that road will have to contend with higher costs and issues they never dealt with in the past. It’s questionable whether EUV lithography will ever be ready for prime time, considering it already missed the 45nm, 32nm, 22nm and now the 14nm process nodes. Cymer made almost heroic efforts to get the power source commercially viable—and now the company is being absorbed into ASML, funded in large part by an investment by Intel. That leaves the rest of the industry facing a future of multipatterning, which has lots of its own issues, or a combination of multipatterning, directed self-assembly, limited EUV and maybe e-beam litho. But even that won’t solve all the issues.
So what’s next? There are lots of options on the table besides shrinking features, particularly when shrinking features no longer reduces costs, improves performance or lowers power. One is die stacking, where only certain parts—logic platforms, for example—get manufactured using the latest processes. There also are different computing strategies involving lots of processors, hundreds or thousands, rather than a central processing unit. And there will be increased research in energy scavenging so power isn’t as much of an issue, coupled with faster throughput on and across die. And finally, there is the option for more and faster customization, and ultimately much more differentiation.
The industry doesn’t come to a standstill just because it doesn’t make sense for companies to shrink features anymore. But it does change, and for most companies that’s not a bad thing. Not even close.