That’s not true on the inside, of course, where radical shifts are under way. The next big push in smart phones will be much greater intelligence. In the iPhone, Siri was just the tip of the iceberg. Future versions are likely to be much more interesting. Add to that the ability to more easily navigate between base stations and to intelligently manage power and performance throughout a battery charge and the changes under the covers will be enormous.

All of this requires far more compute power, much faster signal processing and routing, faster memory throughput, advances in coherency, and much more complex power management schemes. It will even require new architectures, which is why we’re headed down the path of 2.5D and 3D stacked die, pre-integrated subsystems and significant changes in software.

At the other end of the spectrum, these changes are equally prevalent in the data center, where improvements in efficiency and performance are significant enough to be line items on an operating expense budget. The emphasis on NVM Express and PCIe are just the start of what will prove to be a massive change in the way data is managed, stored and shared in the corporate enterprise, and it will require much more sophisticated electronics and software to make it all work.

Where electronics have been in more limited use, it’s far easier to spot what’s changing. In automobiles, for example, the shift from mechanical to electrical has opened up broad new opportunities for improving safety (even though some of this stuff is a distraction to the driver), adding convenience, and improving performance and fuel efficiency. What remains to be seen is ultimately how these inroads by electronics will change automobiles. Will they continue to be differentiated by the car vendors, or will they be differentiated by the makers of electronics the way a company like Apple has changed the music industry?

It’s easy to lose sight of the engineering feats in complex problem solving that enable these advances. It’s also easy for teams that accomplish these feats to lose sight of the bigger picture. All of these changes require an increasingly larger view of the system, big systems based on much more complex little systems, and all working together much more seamlessly than in the past. That means far more standards, more awareness of changes implemented on all levels, and more cooperation between groups that have never actually talked before.

So what will this ultimately mean for SoCs? Will it impede innovation as companies standardize on platforms and subsystems, or will it increase innovation as these platforms are called upon to drive more of the functionality in an ever-larger definition of the system? And who will assume the risk as complexity between groups continues to rise in an increasingly complex supply chain?

The changes on the outside may look like small changes to the consumers using technology, but underneath there is likely to be a lot of churn in all directions as technology continues to improve.

—Ed Sperling

The answer, gleaned from literally dozens of interviews, is beginning to come into focus across the design industry. While software is a great starting point for function, performance, ease of use and integration, it doesn’t have enough structure or stability to dictate designs. In fact, the most stable thing in application software may be the set of application programming interfaces to the operating system. And for operating systems—general and RTOSes—as well as virtualization layers running on Type 1 hypervisors and embedded software, it’s the hooks into the hardware.

But the real value in software isn’t that it’s a stable platform. It’s the opposite. The ability to adapt it for many uses ranging from controlling hardware functionality all the way to managing complex interactions that continually redefine the user experience are what make software so attractive for chipmakers. Software is every bit as important as hardware—but hardware is also every bit as important as software. Some things will always work better in hardware than software, and vice versa.

Coming to grips with this reality is difficult for hardware and software teams, because they often feel threatened by each other rather than part of the same team. Hardware teams worry they will be replaced by software engineers. Software engineers scorn the dictates of hardware, which increasingly are a complex set of somewhat rigid rules governed by process technology, complex flows and the laws of physics.

Both are essential, and both do better working in sync with each other. Designs need to be interlaced between hardware and software from the earliest conceptual phase to the final verification signoff, but they also need to communicate at every step of the design process the way vertically integrated chipmakers would create a design, test it in the fab, then take the results back to tweak the design. The same process needs to happen between hardware and software teams, and there needs to be a methodology for doing that. So far there isn’t one.

Functionality defined by the software needs to be designed in hardware, and then the software has to be able to take advantage of that hardware more efficiently and effectively than if each was written by itself. As an industry we talk a lot about integration being the big challenge, notably re-usable blocks of IP, but integration also needs to be viewed within the design flow and adjusted so that software can be included. For example, battery life in mobile devices can be significantly improved if software engineering teams have some idea of how calls to memory are affecting power utilization. And software performance can be improved if the hardware can execute functions in a specific order, possibly using a dedicated processor core or memory.

It’s time to think of the system as more than just a compilation of parts. Those parts have to be developed as part of the same process, which may force some significant changes in the way things are done and require communication between tools in ways they have never been used before. This is an interesting challenge, and it’s one that needs to be solved for IC design to make the next big steps forward.

–Ed Sperling

The first significant shift is that SoCs are moving mainstream—and mainstream players are moving toward SoCs. Intel announced its intention to become a bigger SoC player several years ago at the Intel Developer Forum, and has begun offering foundry services in a modular approach to other companies building SoCs. That hasn’t amounted to much, so far. But add in a couple other pieces and the picture begins to change. eSilicon has been positioning itself to better control pieces of the supply chain and to document the behavior and characteristics of third-party IP to build complex SoCs. Now Open-Silicon is shifting its focus from ASICs to SoCs.

The big IP players have been busy finding a lucrative niche for themselves, too. Mentor Graphics, Synopsys and Cadence have made big investments in verification IP, as well as other IP they have been buying up and building for the past several years. And companies such as ARM, MIPS, Tensilica and Texas Instruments are battling for sockets in complex SoCs where one processor core is not enough and homogeneous cores aren’t the most efficient.

All of this stuff has to be integrated and connected, too, preferably in a coherent and flexible way. That helps explain the open hostilities between the two leading players in the network-on-chip arena—Sonics and Arteris—and the recent introduction by ARM of its Amba 4 Coherency Extensions (ACE). Connectivity is critical for this whole shift, and the opportunity is very large.

And on the foundry side, GlobalFoundries and TSMC, have been developing developed interposer technology, adding DFM and DFY support for complex SoCs, and slowly building expertise on full 3D integration, which they expect to begin rolling out en masse over the next couple of years.

Each of these moves position these players, as well as startups in places such as China and India, for packaging and stacking of die, the emergence of complex pre-verified subsystems that can be assembled more quickly and cheaply than in the past, and for new services along the way to help create and integrate SoCs. While ASIC design starts have remained flat, the number of design starts for complex subsystems that will be every bit as complex as an ASIC will increase dramatically. That, in turn, will reshape what tools are needed, how they’re sold, and how companies go to market.

Taken in isolation, none of these moves amounts to much more than noise. Over the years there has been plenty of noise, making it hard to decipher real movement from marketing hype. And in a disaggregated industry, moves by one company have to be synchronized with others to be significant. But looked at together, it’s becoming clear that the entire IC ecosystem is in motion and jockeying for change. From here on, things should get quite interesting.

–Ed Sperling

There’s no end in sight, either. Moore’s Law will continue unabated for at least the next several process nodes and demand for new chips is growing in brand new markets such as medical, industrial and automotive. But how we develop these chips will have to change, and that shift will prompt other changes—all of which will have some rather interesting repercussions from the front end of design to verification to back end manufacturing and test.

There are several possible inflection points ahead, each with its ramifications:

1. Lithography. It’s no secret that the current lithography tools aren’t sufficient. Immersion and 193nm wavelength lasers were supposed to have been replaced by extreme ultraviolet lithography at 20nm. The industry will be lucky to see it at 14nm, and it’s certain there will be at least double patterning, and possibly even triple patterning, required at 14nm. Beyond that—the next node appears to be 10nm—either EUV reaches commercial viability or self-assembly templates will replace masks.

IBM says it is close to commercialization of self-assembly. It’s not the first choice. Why disrupt an approach that has served the industry almost since its inception? But without EUV it may be the only choice because double patterning won’t work at 10nm. And that’s where changes begin, from front-end architectural planning of layout and materials and physical effects to design tools to design for manufacturing. In theory, at least, self-assembly may be able to add significant density to designs even at existing nodes.

2. More IP. The amount of commercial IP in designs is growing. Given that these are largely black-box technologies, that will fuel a push toward pre-verified subsystems complete with complex verification IP and hooks into just about every possible configuration and interface imaginable—at least at first.

This all makes sense from a business perspective. Time to market is more critical than building something from scratch that may or may not be as good as what’s commercially available—or at least that’s the theory. But the reality is that to remain competitive chipmakers will have to focus on where they can really differentiate, and that most likely will be in much narrower areas of development—software, analog IP and maybe some digital IP.

3. Stacked die. Some industry experts dismiss stacked die as simply a packaging solution similar to the old system-in-package or multi-chip module. While that’s probably true for the big IDMs, it’s a completely different story for fabless companies, IP developers and interconnect vendors—and for consumers.
Shorter wire distances, the potential to mix and match chips from different process nodes, bigger pipes for signals and lower power to drive those signals all add up to a potentially significant inflection point—and one that could radically change the competitive landscape for companies that can quickly assemble chips for specific markets with different power and performance characteristics and targeted IP.

There are kinks to work out, of course. Who’s responsible if something goes wrong? How do you test die effectively? What’s the best method for cooling these devices? But all of these are being worked on, and most companies involved in the R&D work don’t see these problems as insurmountable.

What’s interesting about all three of these inflection points is that any one of them has the potential to dislocate the industry from business as usual to looking at entirely new approaches. Taken together, they could force even more significant changes because remaining competitive will require innovation that is way beyond the normal way of doing things. And when there is no clear road map, no lane markers, and no standard vehicles to drive, the changes could be well beyond what we expect today and possibly from market sectors and geographies that have never played a significant role in the past.

It may be time to put away the oil can.

–Ed Sperling

The big shift that’s underway isn’t so much a decline in design starts as a rise in SoCs. But SoCs are never really created from scratch. They’re a combination of commercial IP, re-used blocks from previous designs, and some new stuff thrown in. It’s hard to call that a design start. It’s not even certain that’s a derivative. And as we move into stacked die configurations over the next couple years, there will be even less that can be clearly defined.

This is hardly bad news for tools vendors. The increasing complexity of SoCs, versus ASICs or ASSPs, requires more tools and more sophistication on the part of the engineers using those tools. Emulation sales are on the rise. So is the number of classic EDA tools being sold, along with some non-classic ones. And with acquisitions by all of the big EDA players into adjacent markets, it’s not even clear what EDA really is anymore, or whether it should be called EDA.

These kinds of definitions were great for keeping investor interest in EDA in its stock-price boom years, but they will need to be revamped to keep pace with the changes in design. Semiconductor content continues to grow in everything from medical devices to automobiles and consumer electronics. It’s also more complicated than before, requiring more tools to develop, integrate and verify.

But how we define the process of creating semiconductors and how we break it down also can have a big impact on how much money is available for future development. This is an important job, and it’s one that needs to be done collaboratively by the business side of tools companies. It’s also one that needs to be done soon if the industry expects to realize its full potential.

–Ed Sperling

What’s behind this uncertainty is the growing complexity of devices, which has moved design well beyond the comprehension of a single engineer—no matter how good they are or how many pieces they understand—and increasingly even beyond the capabilities of a team of engineers. There are simply too many parts, too many interactions, and too many lines of code to understand it all.

It doesn’t help, either, that IP, subsystems and abstractions are black boxes. No matter how much we try to get comfortable with black-box technology, it still creates an element of doubt that the final product will work as planned. The engineering community is very comfortable with things they understand. They’re far less comfortable taking someone else’s word that it works.

Perhaps even more daunting is the verification piece. With roughly 50% to 70% of the design NRE still in verification—both software and hardware—there is a lot of pressure to reduce costs and cut time to market. Verification is the single biggest target for achieving both. But there also is more to verify, which forces verification teams to rely more on pre-verified IP and software written by other teams who often don’t speak the same language, both from a technology standpoint and literally.

How it all works together is at best an educated guess, and as devices continue to grow in complexity so do the question marks. This isn’t going to get any easier, either, particularly as blocks of IP and software give way to complete subsystems and chips. While this all works better in theory, it also moves the pieces further from the individual engineering teams and re-introduces a virtual silo behavior.

The one link across all of this will be verification. But it remains to be seen just how complete that verification will be, what skills will be necessary for verification teams, and whether the complex products created by an ecosystem really can work flawlessly—particularly in light of some recent failures by some of the most successful IDMs.

–Ed Sperling

To begin with, there’s the question of re-aggregation or disaggregation. While most industries swing back and forth between aggregation and disaggregation, that process has become increasingly unpredictable in the IC business. In part it’s because what we consider a system or a subsystem are changing.

An industry in the midst of a transition is more difficult to digest than one that is stable. The move to stacked die, the rise of a new class of assemblers, and a reconfiguration of the entire supply chain run much deeper than just the acquisitions made in a single year. It will take until the middle of the decade to sort out some of these changes and see which companies maneuver themselves into a better position.

Second, the lines between what’s done in hardware and what’s done in software are blurring. What drives which part of the industry remains to be seen. Hardware companies believe it’s the hardware. Software companies think it’s the software. The truth is probably somewhere in the middle, which is interesting considering neither side speaks the same language or has the same goals.

That will change over the next couple years, and ultimately software and hardware development will be much more synchronized. The real goal is to be able to deliver functions with blazing fast performance and minimal energy consumption. But it’s also going to involve a lot of rightsizing of both hardware and software, something that will become increasingly possible with stacked die because of the shorter distances to memory. In addition, better coordination between hardware and software will allow architects to apportion only pieces of memory—as many bits are are necessary to complete the function in a reasonable amount of time and energy.

Third, the industry has become far more global. Parts that were sourced internally are now being sourced from parts of the world that never played a role in the past. Intel’s recent announcement of a slowdown due to flooding in Thailand is a case in point. With a push to more exotic elements on the periodic table, other disruptions will certainly follow.

On top of that, while startup activity in the United States and Europe is down, it’s booming in places like Israel, Brazil and China. How these companies fare in the future remains to be seen, but geopolitical disruptions can have a big effect on all parts of a system—and the demand for all the pieces within it.

It’s tough enough to follow a mature industry that is progressing in a more or less linear fashion over time. In the next five years the IC industry will undergo significant changes that could render it unrecognizable using today’s benchmarks. After six decades, the IC industry is far from mature and static, which is why it can churn out the most advanced technology the world has ever seen. At least that part seems likely to continue. The rest is all a big question mark.

–Ed Sperling

That’s changing, for several reasons and in several different ways. Expertise is no longer the loss-leader it once was for selling tools. It’s valuable in its own right—more valuable than ever before. And it’s not always available in-house anymore, even in the largest companies.

Reason No. 1: There aren’t enough experts left. The fact that the largest IDMs are now using off-the-shelf standard IP may be the biggest indication that times have changed. The recession of 2008 started things rolling in that direction, and three years later companies still haven’t hired back engineers to pre-recession levels. There simply aren’t enough engineers with deep expertise to go around inside these companies. That’s reason No. 1.

Reason No. 2: Chips are more complex. A chip with 100 million or 1 billion gates at 20nm with multiple power islands, multiple voltages, and possibly built as a 2.5D or 3D stack with legacy analog subsystems created at older process nodes, is beyond human comprehension. It’s well beyond the skill level of even trained teams of engineers who haven’t been working with the latest tools and techniques and doing this stuff day after day. As every engineer knows, getting a feel for a technology takes time and practice. Unfortunately, there are so many different technologies and methodologies in place that no one can get good at all of them. Outside help can fill in the gaps.

Reason No. 3: Time-to-market pressure is escalating. Shorter market windows and compressed internal schedules mean that design teams need to focus on what they can do best and outsource where they add no value or where they’re not considered best-in-class. It’s no longer enough just to buy third-party IP. Someone has to debug it, make sure it’s characterized properly, and integrate it into the design. With a fixed power budget, physical effects to contend with, and lots of other issues to wrestle with, outsourced services are the most cost-effective solution.

External services have changed themselves. They’re not just consultants who used to work in big companies. A lot of these services offerings are tied in with the tools and IP being sold. That’s where the real expertise is. Functional verification expertise is so limited that the real experts in that field know all the other experts. It’s the same for power, packaging, architecture, integration, IP and DFM. The list goes on.
These services also are much more marketable as the industry completes the move from aggregated IDMs to disaggregated to virtual re-aggregation. Supply chains need to move quickly and efficiently, and knowing where to find expertise quickly is essential for survival. And finally, they’re also much more available as discrete offerings than ever before—and specific enough that competition won’t pound down the prices to the point where it isn’t worth charging for.

For decades IBM gave away services while it made its money first on hardware and then on software. Now it makes most of its money on services. The IC tools industry now has a very large opportunity to follow a similar path.

–Ed Sperling

That’s why most of the most far-reaching technology research is being done by universities rather than companies these days, and it’s why most of the stuff being proposed has been in the works for at least a decade or more. Through-silicon vias have been around for years, even though the fine details of how to drill them into CMOS or SOI with minimal impact is still being worked out. But some of the other pieces in 3D are already being used commercially by MEMS makers. And in the case of 2.5D stacking, that approach dates back to the early 1990s with system-in-package and multi-chip modules.

The business side is another matter entirely, and it will drive new technology like never before. This is where the radical changes will come into play, mostly because partnerships will have to be much more tightly integrated so that the supply chain can work as a single entity. That will require someone to take on the role of general contractor, and it’s uncertain whether that will involve a single type of company or whether that role will be more fluid. But one thing is for certain: There will be a struggle to see who can take the biggest share of the pie.

This ultimately will cause a shakeout are various points along the line, too, as companies figure out the next steps. That most likely will involve acquisitions, as struggling companies seek to cash in on a sure thing and larger companies look to gain a foothold more quickly than they could through organic growth. But it also will involve some interesting business arrangements between strong companies, no matter what their size, that can leverage either unique technology and market position and which ultimately will have no choice but to contract the number of companies with which they are working.

At that point, the next wave of competition will begin in earnest, with the goal of getting to market fastest, cheapest and with the most compelling or customized offering for particular vertical markets. If this was a sports competition, we’d now be in the planning stage of the qualifying matches, which will unfold over the next few years. After that, things should get very interesting.

–Ed Sperling

It wasn’t until the past decade when we could actually see atoms. We had to theorize them. And it wasn’t until the past few years when we actually began taking stacked die seriously. But there are some new terms beginning to emerge on the distant horizon, and they indicate not only the marketing opportunities that ultimately may follow but the engineering challenges, as well.

One of the new terms to emerge is “tunnel FETs,” or TFETs. This fits right in with nanowires as a possible technology that will need to be considered for the most advanced digital processes when we begin approaching the next couple nodes following 14nm.

A tunnel FET, according to an Imec research paper, will include multiple horizontal gates, which will be critical for the ultra-low power and ultra-low voltage operation. It also has begun showing up in future projections at TSMC.

Carbon nanowires have been talked about for some time. Research is now beginning to ramp up on this technology. These are extremely thin wires—some even thinner than 1nm—that will be essential when process geometries shrink down to the sub-10nm range. This will create all sorts of interesting effects of course, many of which we haven’t even considered.

While this stuff may seem academic at this point, consider that the major foundries are working on 20nm, with lots of advanced designs in the pipeline at 28nm. Memory is expected to be below 20nm by next year, and work has already begun on 14nm—which for many applications may be the next node after 28nm.

This is the new wrinkle in design. Node skipping has become rampant because of the long tail of derivative designs required by a massive design investment. That economic shift will make these terms more relevant much more quickly, which means what was one distant theoretical research will now become required reading and research for companies looking to stay at the forefront of Moore’s Law. And it will even be relevant for companies working on stacked die that build on these advanced digital platforms.

Research has never had such immediate consequences. The only question now is what those consequences will be.

–Ed Sperling