The big shift that’s underway isn’t so much a decline in design starts as a rise in SoCs. But SoCs are never really created from scratch. They’re a combination of commercial IP, re-used blocks from previous designs, and some new stuff thrown in. It’s hard to call that a design start. It’s not even certain that’s a derivative. And as we move into stacked die configurations over the next couple years, there will be even less that can be clearly defined.

This is hardly bad news for tools vendors. The increasing complexity of SoCs, versus ASICs or ASSPs, requires more tools and more sophistication on the part of the engineers using those tools. Emulation sales are on the rise. So is the number of classic EDA tools being sold, along with some non-classic ones. And with acquisitions by all of the big EDA players into adjacent markets, it’s not even clear what EDA really is anymore, or whether it should be called EDA.

These kinds of definitions were great for keeping investor interest in EDA in its stock-price boom years, but they will need to be revamped to keep pace with the changes in design. Semiconductor content continues to grow in everything from medical devices to automobiles and consumer electronics. It’s also more complicated than before, requiring more tools to develop, integrate and verify.

But how we define the process of creating semiconductors and how we break it down also can have a big impact on how much money is available for future development. This is an important job, and it’s one that needs to be done collaboratively by the business side of tools companies. It’s also one that needs to be done soon if the industry expects to realize its full potential.

–Ed Sperling

What’s behind this uncertainty is the growing complexity of devices, which has moved design well beyond the comprehension of a single engineer—no matter how good they are or how many pieces they understand—and increasingly even beyond the capabilities of a team of engineers. There are simply too many parts, too many interactions, and too many lines of code to understand it all.

It doesn’t help, either, that IP, subsystems and abstractions are black boxes. No matter how much we try to get comfortable with black-box technology, it still creates an element of doubt that the final product will work as planned. The engineering community is very comfortable with things they understand. They’re far less comfortable taking someone else’s word that it works.

Perhaps even more daunting is the verification piece. With roughly 50% to 70% of the design NRE still in verification—both software and hardware—there is a lot of pressure to reduce costs and cut time to market. Verification is the single biggest target for achieving both. But there also is more to verify, which forces verification teams to rely more on pre-verified IP and software written by other teams who often don’t speak the same language, both from a technology standpoint and literally.

How it all works together is at best an educated guess, and as devices continue to grow in complexity so do the question marks. This isn’t going to get any easier, either, particularly as blocks of IP and software give way to complete subsystems and chips. While this all works better in theory, it also moves the pieces further from the individual engineering teams and re-introduces a virtual silo behavior.

The one link across all of this will be verification. But it remains to be seen just how complete that verification will be, what skills will be necessary for verification teams, and whether the complex products created by an ecosystem really can work flawlessly—particularly in light of some recent failures by some of the most successful IDMs.

–Ed Sperling

To begin with, there’s the question of re-aggregation or disaggregation. While most industries swing back and forth between aggregation and disaggregation, that process has become increasingly unpredictable in the IC business. In part it’s because what we consider a system or a subsystem are changing.

An industry in the midst of a transition is more difficult to digest than one that is stable. The move to stacked die, the rise of a new class of assemblers, and a reconfiguration of the entire supply chain run much deeper than just the acquisitions made in a single year. It will take until the middle of the decade to sort out some of these changes and see which companies maneuver themselves into a better position.

Second, the lines between what’s done in hardware and what’s done in software are blurring. What drives which part of the industry remains to be seen. Hardware companies believe it’s the hardware. Software companies think it’s the software. The truth is probably somewhere in the middle, which is interesting considering neither side speaks the same language or has the same goals.

That will change over the next couple years, and ultimately software and hardware development will be much more synchronized. The real goal is to be able to deliver functions with blazing fast performance and minimal energy consumption. But it’s also going to involve a lot of rightsizing of both hardware and software, something that will become increasingly possible with stacked die because of the shorter distances to memory. In addition, better coordination between hardware and software will allow architects to apportion only pieces of memory—as many bits are are necessary to complete the function in a reasonable amount of time and energy.

Third, the industry has become far more global. Parts that were sourced internally are now being sourced from parts of the world that never played a role in the past. Intel’s recent announcement of a slowdown due to flooding in Thailand is a case in point. With a push to more exotic elements on the periodic table, other disruptions will certainly follow.

On top of that, while startup activity in the United States and Europe is down, it’s booming in places like Israel, Brazil and China. How these companies fare in the future remains to be seen, but geopolitical disruptions can have a big effect on all parts of a system—and the demand for all the pieces within it.

It’s tough enough to follow a mature industry that is progressing in a more or less linear fashion over time. In the next five years the IC industry will undergo significant changes that could render it unrecognizable using today’s benchmarks. After six decades, the IC industry is far from mature and static, which is why it can churn out the most advanced technology the world has ever seen. At least that part seems likely to continue. The rest is all a big question mark.

–Ed Sperling

That’s changing, for several reasons and in several different ways. Expertise is no longer the loss-leader it once was for selling tools. It’s valuable in its own right—more valuable than ever before. And it’s not always available in-house anymore, even in the largest companies.

Reason No. 1: There aren’t enough experts left. The fact that the largest IDMs are now using off-the-shelf standard IP may be the biggest indication that times have changed. The recession of 2008 started things rolling in that direction, and three years later companies still haven’t hired back engineers to pre-recession levels. There simply aren’t enough engineers with deep expertise to go around inside these companies. That’s reason No. 1.

Reason No. 2: Chips are more complex. A chip with 100 million or 1 billion gates at 20nm with multiple power islands, multiple voltages, and possibly built as a 2.5D or 3D stack with legacy analog subsystems created at older process nodes, is beyond human comprehension. It’s well beyond the skill level of even trained teams of engineers who haven’t been working with the latest tools and techniques and doing this stuff day after day. As every engineer knows, getting a feel for a technology takes time and practice. Unfortunately, there are so many different technologies and methodologies in place that no one can get good at all of them. Outside help can fill in the gaps.

Reason No. 3: Time-to-market pressure is escalating. Shorter market windows and compressed internal schedules mean that design teams need to focus on what they can do best and outsource where they add no value or where they’re not considered best-in-class. It’s no longer enough just to buy third-party IP. Someone has to debug it, make sure it’s characterized properly, and integrate it into the design. With a fixed power budget, physical effects to contend with, and lots of other issues to wrestle with, outsourced services are the most cost-effective solution.

External services have changed themselves. They’re not just consultants who used to work in big companies. A lot of these services offerings are tied in with the tools and IP being sold. That’s where the real expertise is. Functional verification expertise is so limited that the real experts in that field know all the other experts. It’s the same for power, packaging, architecture, integration, IP and DFM. The list goes on.
These services also are much more marketable as the industry completes the move from aggregated IDMs to disaggregated to virtual re-aggregation. Supply chains need to move quickly and efficiently, and knowing where to find expertise quickly is essential for survival. And finally, they’re also much more available as discrete offerings than ever before—and specific enough that competition won’t pound down the prices to the point where it isn’t worth charging for.

For decades IBM gave away services while it made its money first on hardware and then on software. Now it makes most of its money on services. The IC tools industry now has a very large opportunity to follow a similar path.

–Ed Sperling

That’s why most of the most far-reaching technology research is being done by universities rather than companies these days, and it’s why most of the stuff being proposed has been in the works for at least a decade or more. Through-silicon vias have been around for years, even though the fine details of how to drill them into CMOS or SOI with minimal impact is still being worked out. But some of the other pieces in 3D are already being used commercially by MEMS makers. And in the case of 2.5D stacking, that approach dates back to the early 1990s with system-in-package and multi-chip modules.

The business side is another matter entirely, and it will drive new technology like never before. This is where the radical changes will come into play, mostly because partnerships will have to be much more tightly integrated so that the supply chain can work as a single entity. That will require someone to take on the role of general contractor, and it’s uncertain whether that will involve a single type of company or whether that role will be more fluid. But one thing is for certain: There will be a struggle to see who can take the biggest share of the pie.

This ultimately will cause a shakeout are various points along the line, too, as companies figure out the next steps. That most likely will involve acquisitions, as struggling companies seek to cash in on a sure thing and larger companies look to gain a foothold more quickly than they could through organic growth. But it also will involve some interesting business arrangements between strong companies, no matter what their size, that can leverage either unique technology and market position and which ultimately will have no choice but to contract the number of companies with which they are working.

At that point, the next wave of competition will begin in earnest, with the goal of getting to market fastest, cheapest and with the most compelling or customized offering for particular vertical markets. If this was a sports competition, we’d now be in the planning stage of the qualifying matches, which will unfold over the next few years. After that, things should get very interesting.

–Ed Sperling

It wasn’t until the past decade when we could actually see atoms. We had to theorize them. And it wasn’t until the past few years when we actually began taking stacked die seriously. But there are some new terms beginning to emerge on the distant horizon, and they indicate not only the marketing opportunities that ultimately may follow but the engineering challenges, as well.

One of the new terms to emerge is “tunnel FETs,” or TFETs. This fits right in with nanowires as a possible technology that will need to be considered for the most advanced digital processes when we begin approaching the next couple nodes following 14nm.

A tunnel FET, according to an Imec research paper, will include multiple horizontal gates, which will be critical for the ultra-low power and ultra-low voltage operation. It also has begun showing up in future projections at TSMC.

Carbon nanowires have been talked about for some time. Research is now beginning to ramp up on this technology. These are extremely thin wires—some even thinner than 1nm—that will be essential when process geometries shrink down to the sub-10nm range. This will create all sorts of interesting effects of course, many of which we haven’t even considered.

While this stuff may seem academic at this point, consider that the major foundries are working on 20nm, with lots of advanced designs in the pipeline at 28nm. Memory is expected to be below 20nm by next year, and work has already begun on 14nm—which for many applications may be the next node after 28nm.

This is the new wrinkle in design. Node skipping has become rampant because of the long tail of derivative designs required by a massive design investment. That economic shift will make these terms more relevant much more quickly, which means what was one distant theoretical research will now become required reading and research for companies looking to stay at the forefront of Moore’s Law. And it will even be relevant for companies working on stacked die that build on these advanced digital platforms.

Research has never had such immediate consequences. The only question now is what those consequences will be.

–Ed Sperling

While that basic theme has been argued throughout the history of civilization—smart people are supposed to learn from other people’s mistakes, not just their own—there’s an interesting twist when it comes system-level design. We are using the same technological approaches developed decades ago. In fact, we’re using some of the same ideas created centuries ago when it comes to the binary system. But we’re using it differently, and we’re getting infinitely better about how we use it.

The content is still garbage. We’re still recycling plays from ancient Greece and the late 1500s, and if you were to tune in to the majority of messages on instant messenger, Twitter, Facebook, and all the other international versions, it’s still useless drivel. It’s nice that people are brushing their teeth and taking a shower, but the rest of the world doesn’t need to know that.

Still, the approach to delivering that content, no matter how bad the subject matter, is changing. IBM invented virtualization back in the 1960s in mainframes to better utilize its processing capacity (and the scientists developing the first atomic bomb in New Mexico did something similar back in the 1940s), but now we’re using a similar approach to turn on and off many cores rather than worrying about bottlenecks of trying to fit all processing onto one. They’re there when you need them, quiet when you don’t. We’re also personalizing data delivery and making it mobile, for better or worse.

And while systems used to be a collection of discrete chips, they’re heading back in that direction again with stacked die. The difference is they now will have much higher bandwidth and a much more rational and flexible use of energy, memory, processing power. Over the next few years, designs will be much more granular and programmable, as much dependent on the software as the hardware, and ultimately defined by the user’s needs. Even the manufacturing of these chips is getting more granular, with atomic-level control of doping now very much a reality. These may be small steps—in fact, the steps may be on the nanometric or even picometric scale—but they add up to a very significant shift, and a very interesting one.

If SoCs can be built with this much control, then the convergence of almost everything that we have developed in decades of electronics can be carried around in your pocket without depleting an increasingly thin battery. There will even be some new tweaks thrown in, such as rock-solid security and privacy controls. Most of the content will continue to be garbage, of course. That never seems to change. But at least we’ll be able to experience it in new ways, in new places, and for much longer periods of time—and enabling that makes all of our lives much more interesting.

–Ed Sperling

What we’re witnessing isn’t just the return to a collection of chips on a board that were put there because they couldn’t be incorporated into the main logic chip. Instead, this is a well-thought-out, extremely granular approach to what goes where. In many cases, it will be cost that drives these decisions. But at least part of the business decision will be an understanding of how to get processing done the most effectively and with the least amount of energy. In essence, you only add what you need.

Think about a smart phone, for example. The key challenge there is battery life, not performance. If you don’t plug it in at night, or you run applications with lots of graphics, your phone begins showing the red bar of death. Continue using it at your own peril. In this type of setting, the market has been almost exclusively ARM- or MIPS-based. In the future, it could well be based on multiple chips, including Intel-based SoCs, as more performance is added into these devices to make them more useful.

This trend is particularly evident in tablet devices such as the iPad, where streaming video processing is required and where search needs to be sufficiently fast, but where battery life also needs to be sufficient to last through a long user session. In this case both performance and energy efficiency are required, often at a very granular level depending upon user preferences. Instead of an ARM or MIPS processor for efficiency, the ARM or MIPS processors may be the main performers, coupled with an ARC processor or Tensilica DSP for audio and an Intel processor for efficient search.

The semiconductor industry historically has used general-purpose processors with customized software and IP. In the future, designs likely will entail a combination of much more tailored processors that more effectively use even more tailored software and IP. And as simple as this sounds in theory, the impact will be enormous for everyone involved—from design to verification to manufacturing to the end users of the devices.

–Ed Sperling

This is an interesting shift, and one not seen in EDA since the booming 1990s. Since then, selling more seats has been a challenging proposition, to put it mildly. Most customers have tried to eke another generation of chips of out their tools, delaying and delaying their purchases, and prompting heavy investment by EDA vendors in “adjacent” markets.

Apparently the chipmakers can delay their tools purchases no more. Complexity has gone through the roof, particularly with software integration and power issues, and time-to-market with a functional chip that can yield sufficiently and also uses less energy has become a particularly vicious cycle. Throwing engineers at the problem armed with spreadsheets and tools that take days to simulate instead of minutes isn’t an effective solution. Throwing outdated point solutions at system-level problems doesn’t work, either.

The question now is whether this begins to spread downstream into midsize fabless companies, particularly with 2.5D, and whether this also creates momentum for the kinds of cloud-based debug solutions proposed by Synopsys, Cadence and Mentor. Selling more new tools to large customers is a good business, but hedging it across multiple sectors is even better. And better yet, it would provide fuel for an extensive re-investment in tool development as EDA companies begin battling for increasingly lucrative market share.

After more than a decade of relatively flat performance, EDA apparently is being recognized as critical again—and not a moment too soon.

–Ed Sperling

In the past it was technology first, business last. We are now at the stage where it is business first, technology last. Re-use of entire die as subystems, better use of design resources, predictable yields on older technologies and the ability to not have to re-design analog or standard IP at advanced nodes can provide enormous dollar savings to developers.

That doesn’t mean that technology gets left in the dust, of course. Wide I/O and shorter wires, rationalization of how memory gets used, connecting cores directly to memory bits and matching the needs of specific applications with right-sized processors are all important advances in SoC design. Performance can be boosted significantly, power can be cut and best-of-breed IP can be developed or purchased to make these chips even better.

But all of this has to be weighed against cost—including hidden costs such as time to market and fuzzy costs such as yield. The real formula to consider here is time to profitability and that will depend on a number of factors. Interposers in 2.5D stacks, or TSVs in true 3D stacks, need to be perfected and commoditized. Drilling through a thinner piece of silicon isn’t simple stuff. Understanding the impact on physical stress is still incomplete, and none of this has been done over time.

In addition, packaging needs to be competitive with existing packages—if not exactly in price, then at least close enough. Time to market with sufficient yields needs to be proven. Full characterization of IP and subsystems needs to be completed for a variety of implementations—particularly in stacks—to avoid nasty physical effects. And IP vendors need to make the necessary investment to make this happen. Moreover, standards need to be developed, particularly in areas such as layout and business responsibility and liability to make sure this all goes smoothly.

None of this will happen overnight, and some of it may be a chicken-and-egg decision where companies hold back on their investment until they see others taking steps in this direction. Market timing, yet another business element, is very important. But if the business of technology is to move forward, the business itself will have to make some important commitments. And in this case, time is of the essence.

–Ed Sperling