Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking.

Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers.

So what’s behind these move? In TI’s case, there appears to be a recognition that if analog can be put on a separate die then TI will be able to offer full subsystems or chips for specific vertical markets. When you think about it, that’s a lot more profitable than a team of engineers trying to retrofit analog functionality on 28nm or 22nm processes. Analog processes can survive for 10 years or more. Digital processes are turned over at the rate of Moore’s Law.

In the early part of the 00 decade, analog companies had largely given up on mixed signal processors because they were too hard to integrate. They changed their minds in the latter part of the decade as the smart phone revolution drummed up enough demand to warrant the investment. But the future appears to be a return to separate chips bound together by either a silicon interposer or through-silicon vias.

That makes analog designers far more important than they were a year ago, and it makes them far more valuable. TI hasn’t paid this much money for analog talent since it bought Burr-Brown in 2000 for $7.6 billion.

In Microsemi’s case, microwaves are becoming much more popular for advanced communications—particularly in the military space where terahertz clock frequencies are under development. At these kinds of speeds signal integrity is a challenge using standard RF technology.

What’s making these terahertz frequencies possible is a new metal-insulator-insulator-metal stack—a not-so-simple concept when you consider these designs suffer from some of the same kind of thermal issues as other stacked die. Putting two insulation layers together can create heat problems that require some sophisticated venting concepts.

We expect to see more consolidation in both of these spaces, and far more vertical solutions that can be quickly assembled with other die to reduce time to market significantly. While these are large sums of money, the acquisition frenzy appears to be just getting started.

–Ed Sperling

The old definition of a good chip was that it could be manufactured with reasonable yield, it was functionally solid, and it performed at least as well as the market demanded. That definition is changing, however.

There will always be a difference between ‘good’ and ‘good enough.’ We all want to own the ‘good’ chips in our electronic devices. But what’s noteworthy are the changes under way on the ‘good enough’ side and how they compare with the ‘good’ chips.

One change, of course, is the increased reliance on software. If the device isn’t life-critical and it can be fixed with a software patch—or if it’s a consumer device that will be replaced within a year or two—then a few glitches aren’t considered that important. The phone function still has to work on a smart phone, but it doesn’t necessarily have to work better than another phone. And the Internet access on a phone isn’t expected to be as good as a desktop connected via Ethernet.

A second change is that in some markets time to revenue is considered more important than great engineering. While advanced chip companies continue to invest in some of the best power-saving techniques for prolonging battery life, many OEMs that buy the chips and assemble them into final products don’t take advantage of those features. Or more accurately, they willfully ignore those features because it takes to long to optimize them.

Third, just having functionality is good enough in some markets even if it’s not the best implementations of those functions. As long as they work that’s considered good enough. The differentiator isn’t the technology. It’s the availability of new products. Even in the IP market, best of breed isn’t always as important as integrated and tested. The financial risk of getting it all wrong with all the best IP is huge when 70% or more of the chip is reusable or purchased IP. In fact, that’s potentially more costly than losing some market share to superior engineering.

There are pendulum swings in IC design, as there are in all markets. Companies that go for ‘good enough’ and that compete on price and time to market historically have run their course and been burned. What’s changed is that with complexity affecting even the best-run companies—witness Apple’s antenna problem, Intel’s Sandy Bridge chips and a long line of overheating batteries from multiple vendors—good enough isn’t always less reliable. In some cases, good enough may actually be better.

–Ed Sperling

The number of system-level design flaws is rising, and they’re not just little mistakes. These are high-profile errors that are making headlines all over the globe.

While it’s debatable whether Toyota’s problem was a hardware or software design glitch, the simple fact is there was a design flaw somewhere. That’s true for the BP Gulf of Mexico leak, regardless of who’s responsible for maintaining a drilling platform. And it’s no different for the Japanese nuclear plants, which were built too close together and designed with insufficient backup power.

Closer to home, Apple’s iPhone antenna design was flawed. So was Intel’s initial Sandy Bridge chip.

So what do all of these problems have in common? Engineers have long argued that they can engineer a solution for just about anything. They’re probably right, given the appropriate resources, an understanding of all possible scenarios and a well-defined set of conditions. But at the system level—and that includes everything from ICs to full-blown industrial facilities—rising complexity, time-to-market and cost pressures, and the inability of engineers to verify and predict everything that can go wrong in a given amount of time are causing everything from minor nuisances to full-blown disasters.

Looked at individually, these look like unrelated errors. Looked at together, however, they point to a much broader problem across the entire supply chain, from design to manufacturing. Things we have taken for granted, largely as a result of years of slow evolutionary tweaks, now require more radical reassessments. That includes everything from the tools being used to design and create systems to budgetary considerations about what can be cut and what areas need additional resources. Inside of many companies these kinds of decisions are highly politicized, and something clearly isn’t working.

This kind of reassessment needs to run end to end. If there’s a problem at the back end, chances are good that the initial design was flawed and that the people doing the design didn’t have the right kind of training. In the case of Apple and Intel, the problem wasn’t so much cost cutting as unbelievable complexity and aggressive schedules. Tools do exist to solve some of these problems, but it takes time to train people to use them and to understand their benefits—something verification engineers have been complaining about for the past decade.

Unfortunately, we will probably see more of these engineering mishaps in the future. It takes awhile for executives at public companies, who are used to living quarter by quarter, to recognize the full financial impact of not addressing these problems properly. This isn’t a new issue, either. The old adage of, ‘Penny wise, pound foolish,’ dates back to the mid-1600s.

But it’s also time for engineering teams to reassess what they do, how they verify it, and what’s considered good enough—and not good enough. While an antenna problem can be fixed with a case and improved in the next release, it’s a lot harder when the system is mission-critical and affects lives. Nevertheless, there are costs for both. Consumer trust takes years to build, but in the Internet era it can be destroyed in a matter of days.

Perhaps even more daunting, the cause of these problems can stem from outside of a company. A complex ecosystem of parts means that a company is only as good as its partners and its quality control procedures for third-party IP. If it doesn’t work right it’s the chipmaker’s problem. And in the case of fabless semiconductor companies, it might even be a glitch in the manufacturing process.

Getting all of this right starts with a great concept and a flawless design, but it doesn’t stop there. It’s now all about the system, and the definition of the system and what can go wrong inside that system are growing.

–Ed Sperling

Across the semiconductor industry—as well as many other end-product industries—there have been some well-documented and sober assessments of what impact the damage in Japan will have on business.

In the EDA business, these kinds of numbers will be much harder to determine. Japan is a big consumer of EDA tools for the leading-edge process nodes, but with disruptions in power it will be difficult for Japanese companies to keep their simulation and verification farms on schedule. That will cause a slowdown at the front end of the flow all the way back to the architectural modeling stage. How long that slowdown lasts ultimately will determine what tools these companies buy and when.

Most of these chipmakers have foreign offices, but transferring operations to those offices takes time. Even utilization of cloud-based infrastructures will take time. These are just being mapped out by major EDA companies. Ramp-up time will be measured in months, at best. Moreover, those kinds of shifts will require some significant attitude changes among chipmakers about sending proprietary data to an outside company—something they have been reluctant to do in the past.

Professional services to help with these kinds of very complex transitions also are likely to be in significant demand once Japanese companies regain their footing. The question is whether enough expertise can be provided by existing companies to bridge the gap until Japanese companies are back to normal, or whether those kinds of services will have to be augmented with additional skills, training and hiring, which will slow down the whole process.

For Japan, this is like running a competitive race with leg weights. The sheer magnitude of the devastation means that even the best-crafted disaster plans don’t suffice. That raises short-term questions about the effect on the overall Japanese chip industry, as well as long-term issues about what solutions it will choose. And that ripples back into the EDA world, where different scenarios are under discussion about how to best serve their Japanese partners—and how those partners are likely to fare. There are chipmakers in other regions of the globe, including South Korea, China, Taiwan, and even North America and Europe, that are running these scenarios, as well, trying to figure out just what this means to them.

There are no clear answers here, just as there are no clear answers inside of Japan about when the crisis will subside. But there certainly are a lot more questions being asked.

–Ed Sperling

It’s probably too harsh to say that multicore has been a failure, but it’s flat-out wrong to say it has been successful.

Multicore was an inevitable outgrowth of Moore’s Law. You simply can’t keep turning up the frequency for processors at advanced nodes without cooking the chip into oblivion. In theory, four cores running at a much cooler 1GHz should be better than one core running at 3GHz. By that thinking, 20 cores should be even better.

There are two main problems with that reasoning, however. First, most software isn’t suitable for parallel computing. Databases and embarrassingly parallel applications such as graphics and some scientific calculations work best. So do some of the EDA design tools. But the majority of applications that people use can’t be parsed out to more than a couple cores—generally two and no more than four—and they can’t be scaled as more cores are added to each new node.

Second, memory becomes a bottleneck when it’s shared by cores. The problem with using approaches such as virtualization across a multicore chip is that they’re all sharing a common memory. Even when memory is split up into multiple discrete segments, there is still a challenge to keep everything straight—and one that is hardly scalable for many more cores.

There are other issues, as well. Being able to quickly turn on and off cores requires at least some power to keep them operating. In addition, making all the cores the same size to handle any available application is an inefficient approach. A simple executable file doesn’t require as much energy for processing PowerPoint or Excel, but it may require more speed than e-mail.

The solution—and one that is gaining traction across the design world—is a different approach to using these cores. If the software applications cannot be written in parallel and written to scale, then why force the issue? The alternative is to design cores for specific applications or functions, each with its own block of memory—or at least with a wider I/O to reach that memory.

Wide I/O, whether it’s a transposer or a through-silicon via, is a major shift in thinking for how SoCs are designed. It’s not just about the I/O. It’s about the functioning of many parts of the chip, whether that’s a collection of processor cores in a single place or scattered around the SoC, and whether they’re the same or different. It’s also a recognition that the old approach of designing hardware as one-size fits all doesn’t benefit the application’s function, performance, or the amount of power that’s wasted in delivering that performance.

These are subtle changes in thinking, but the results will create a profound shift across hardware design for years to come.

–Ed Sperling

Selling EDA through a software-as-a-service model is hardly a new concept. It’s also not a particularly successful one. Despite some initial hype and sporadic attempts to revive it, the idea has fallen flat due to concerns about version control, security and an almost universal aversion to engineers having to send large files back and forth to a server.

The approach is getting a new look, however, although less from the software-leasing side and more from a cloud-based resources type of scheme. There are several things driving this change:

First, the sheer complexity of new designs has greatly bumped up the need for additional resources to complete these designs. Even the most advanced chip companies working in the wireless communications space are complaining that they don’t have enough resources to run simulation, synthesis and verification. Everything is already multithreaded and multiprocessing, and it’s still not enough processing power.

Second, that complexity is creeping into designs even back a couple of nodes on the Moore’s Law road map. The companies that were working at 180nm and 130nm are now dealing with designs at 90nm and 65nm. That has driven up the need for new tools, but the low margins on their designs are forcing them to consider alternatives to buying tools. This explains why companies like Altium and Physware are now offering cloud-based services, and why even the largest EDA players are starting to revisit this approach.

Third, the infusion of more software into chip design has further boosted the need for additional resources, particularly emulation boxes. Because software teams typically don’t have the budget for these kinds of machines they have been scheduling time when the hardware team isn’t using them. The problem is that the hardware teams now need more resources to handle more complex designs, which may force the combined teams to look for those resources elsewhere. Cloud is a logical extension.

3D stacking will only exacerbate the resources shortages when it begins hitting the market in late 2012 or 2013. At that point either there will be a boom in EDA tools sale or in EDA tools rentals, or both. And there may be a mad scramble to assemble the infrastructure as these changes unfold.

–Ed Sperling

Every now and then you get the feeling you’ve been here before, and with technology this is a persistent theme.

Virtualization looks remarkably similar to time sharing, which is what most engineers in their 40s and 50s used when they were in college. And 3D stacking, particularly the 2.5D version, looks eerily like the old MCM, aka multi-chip module.

There’s nothing wrong with resurrecting old concepts and putting a new spin on them. Shakespeare did it. So did Apple with the iPod and the iPad. And current system-level design approaches have been talked about for the better part of a decade.

What’s different is how all the pieces go together to make something successful. Timing is everything, and in technology it’s more than just end-market acceptance. It’s a tightly integrated ecosystem with interplay between different tools, different manufacturing processes, design flows and various levels of abstraction. In the future, it also will be about being able to bridge multiple process generations on stacked die into a single package or even a single chip.

All of this will require a combination of new technologies, such as TSVs and TSV interconnect models, tools to bridge several generations of analog and digital, a deeper understanding of how software will utilize the hardware, and a far better understanding of how IP needs to be characterized and verified. But on a more mundane level, it also will require integration of existing generations of tools with each other so that high-level synthesis and software prototyping can work effectively in existing hardware, software and manufacturing flows.

These are tall challenges, and no one company can do it alone. Done in unison, the market can expand at an accelerated rate—even drawing in new customers, which is something the EDA industry has been desperately searching for. But so far the efforts in this respect have been rather paltry, driven more by standards organizations than by tools vendors themselves.

Customers have been asking for more integration, and vendors have been looking for measurable ROI to make that happen. But the real ROI may be much bigger than the cost of the integration itself and raise top-line revenue for years to come. In an interconnected and interdependent world, what’s good for one company has to be good for multiple companies.

–Ed Sperling

For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm.

That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed off by one node the way strain engineering and immersion and double patterning have managed to rescue bulk CMOS and lithography, respectively, for several nodes.

Second, it means that the problems that have been averted at 22/20nm will be piled up with other problems that have been averted. For the most advanced chip developers working at the bleeding edge of Moore’s Law, this is not good news.

The unanswered question is just how much of the industry will be reeling from this bad news. Memory makers and Intel will certainly feel the pinch, and so will some of the high-volume smart-phone chipmakers, but if 3D stacking lives up to its promise the bigger issues may be well outside the physical layout and process world. They may be in areas such as IP integration, software development and integration, packaging, self test and correction, and verification.

The schism that is developing may no longer just be between the big and the small and the haves and the have nots. It may be between those with big physical problems, and those with virtual problems, and size may no longer be the key differentiator between a company that’s highly profitable and one that’s not, or between those able to wield the most leverage and those that can’t.

–Ed Sperling

It used to be easy to define a system. It was an ASIC, an ASSP or even an SoC. Increasingly, however, that definition isn’t nearly broad enough.

With power issues now spreading across an entire device and software being used to manage everything from embedded applications to board-level functionality, the system is now much bigger than a single chip or even a system in package. It now encompasses software, hardware, IP and firmware. And in the case of communications, it can reach even beyond the device itself.

This creates problems at the architectural, design and verification level. More has to be thought about up front, and it has to be able to be verified further downstream. But it also creates a huge opportunity for the EDA industry, which has been relatively flat for the past few years. Rather than just competing for a bigger piece of the same pie, the opportunity is to compete for a piece of a much bigger pie.

It also creates a new challenge, and some big questions that have yet to be answered. While hardware companies are accustomed to paying for EDA tools and IP, software companies are not. And in places like China, even FPGA tools are considered expensive so many lesser-quality freeware tools are in use by indigenous startups.

What isn’t known yet is who will actually gain control of this design and development process in the future. Will it be the hardware engineering managers, who can easily justify an investment in tools, or will it be the software engineering managers who are reluctant to spend? And will it happen in places like Taiwan, Europe and North America where tools are considered an effective alternative to expensive labor, or in places like China where time to market may be perceived as reliant on a large labor pool rather than better tools?

What is clear is there is money on the table for those companies come up with the right solution to bigger design challenges and which can price it accordingly for whichever segment comes out on top. But there are still a lot of unanswered questions about exactly what those challenges will be, who will be facing them and who will be paying for them.

–Ed Sperling

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process.

To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes mature and using standardized ASIC platforms becomes an option.

So far the answer isn’t clear, and it may not be the same for all fabless companies or at all stages of the 3D rollout. While IDMs will continue to develop most of the parts themselves, the big advantage of 3D is that fabless companies will be able to focus on what they do best and work around more standardized underpinnings. In planar chips that requires tweaking the base platform, which has made FPGA prototyping extremely popular. In 3D, that tweaking may be possible on a completely separate die and sometimes even in software, all of which will run atop a standard platform containing memory, a processor and the I/O.

This is a multi-year rollout, of course. The first chips from non-IDMs, which are expected to begin showing up in 2012, will likely be two layers. Those will be followed by three or more layers of silicon, all connected with through-silicon vias. During that time, ASIC platforms will become commoditized and standardized and FPGAs will have to follow the same route. In fact, it may be likely that FPGA prototyping will be replaced by FPGAs as part of the overall 3D structure if the programmable logic approach will succeed.

There is plenty of opportunity in this shift, and for EDA companies this may be the inflection point they have been waiting for. While they have had trouble competing with FPGA vendors, which subsidize their tools as part of the cost of the FPGA platform, the market for FPGA prototypes will likely remain flat or shrink as 3D stacking gains steam. And the complexity of 3D structures, complete with thermal and mechanical stress and power issues may dwarf the ability of layout tools that have become popular in FPGA floorplanning.

So far no one knows for sure what will happen in this market. But the writing is on the wall that change is coming, and in every change there are winners and losers. The only question is who’s going to be on which side.

–Ed Sperling