Change is rarely something people can grasp, particularly in technology. Unless it involves a completely new way of doing things—witness the PC, the cell phone and the Internet, for example—most change involves evolutionary improvements.

This is the proverbial frog in a pot of boiling water. Heat the frog up slowly and it will cook. Throw the frog into boiling water and it will leap to safety.

Changes at the chip level are even harder to discern than they are at the end device level. We have been using bulk CMOS for decades, following Moore’s Law since 1965, and working with automation tools that in some cases have been around for nearly 20 years. Everything has improved significantly, of course, or else we’d never be able to design SoCs with 100 million gates or processors with a billion or more gates.

But the next real growth in the tools world will come not from a specific inflection point at a process node. It will come from an understanding of how business is intersecting with technology, breaking down silos on both sides. While technology has always been driven by money—Moore’s Law is, to a large extent, an economic statement after all—the two worlds have been remarkably self-contained. Aside from squeezing every last penny out of a design, a package, a substrate or a manufacturing process, the design process really hasn’t been about understanding how technology and business can really work together.

That will change significantly in stacked die—a first step toward merging those two worlds—as well as in the areas of optimizing hardware and software to improve performance and reduce power. Some of the approaches are well tested. Multi-chip modules and system-in-package approaches have been around for years, for example, even though the business drivers have changed significantly to make them far more popular. Being able to re-use analog or customize a multi-die implementation with MEMS or sensors is a radical shakeup in the barriers that have existed between these areas of expertise. Likewise, being able to harness only the resources that are necessary is well understood, but applying those same concepts to extending battery life or improving performance for a specific application is a radically different approach than making everything work with a general-purpose processor.

We may well be dealing with the same frog and the same pot of boiling water, but the real opportunity may be in understanding exactly how hot the water needs to be, how large the pot is, when the heat is best applied, how much that will cost, and whether you really need to cook the frog in the first place.

–Ed Sperling

The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the charge.

This is the first of several major shifts that will begin over the next few process nodes. One will involve lithography, where double patterning and computational scaling will become more prevalent starting at 22nm. The second involves the proliferation of lots more 3D structures on wafers, including everything from multi-gate transistors such as Intel’s tri-gate FinFETs to MEMS devices and 3D memory. A third involves stacking of die, which is expected to bridge multiple process nodes together initially, with more complete modeling and the proliferation of through-silicon vias over time.

What’s becoming clear is that we’ve just scratched the surface when it comes to power and performance. Wide I/O, right-sized processor cores, more efficient software, co-development of hardware and software and better connectivity externally and internally will provide significant boosts in performance while also cutting power consumption. There are huge gains to be made over the next couple nodes in both areas.

What few people are talking about, however, are the physical effects that need to be considered in developing this new breed of chips. Time-to-market pressures will force much more re-use, more concurrent design and more experimentation with new ways of making that happen faster. But in the rush to get chips out the door, there will be all sorts of new challenges to deal with. How do EMI and ESD change in a chip that is densely packed with FinFETs, for example? How do vertical stacks and vertical structures affect noise-sensitive analog IP? And what happens when you start mixing firmware, software and hardware with third-party IP? How does all of this affect timing closure? And what sort of impact will there be from turning on and off segments of a chip that may include lots of 3D structures in a 3D stack?

We have come a long way in verifying the functional aspects of SoCs. The next big challenge will be understanding the physical effects and how to model them effectively. The introduction of FinFETs is a major step forward, but we still have a long way to go to really understand how all the pieces fit together.

–Ed Sperling

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent.

To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC, this represents a huge shift—and opportunity. It’s an entry point into the fast lane that previously was dominated by ASICs, with performance and power overhead muted by shorter distances and wide I/O connections to memory chips.

For EDA vendors, the real upside of 3D is around the edges of the technology, and in the potential that new customers will require new tools. Mentor’s push into 3D test is a case in point. Cadence’s integration push will likely fit into this scenario, as well. And the push by Synopsys deeper into the IP world will likely find new growth potential in 3D. There’s also an opportunity for exploring everything from thermal impacts of different IP to 3D topographical layout tools. But the real hope in EDA is that when companies begin putting together 2.5D and 3D packages based on pre-integrated blocks of IP, or possibly even fully integrated die, that complexity will drive customers to start buying more advanced tools.

For the supply chain as a whole, 3D offers a new challenge. It’s a matter of working with partners more closely than in the past—possibly new partners—to deal with more choices and significantly more complexity. This is easier said than done, because understanding a partner’s real strengths won’t be apparent until stacking die becomes a more mature solution. There are risks inherent in any partnership, and there are costs of going to market even with the right partners. But with stacked configurations, those costs are multiples of what they might be in 2D layouts.

–Ed Sperling

If you really want to know what’s going on inside the IC design world, pick up a copy of the annual reports of the largest foundries. Then triangulate that with the earnings reports of the largest makers of computers and mobile electronics and the makers of EDA tools and IP.

All three areas are experiencing a massive uptick, which is good news considering the travails of the past couple of years. The problem is that retooling in each sector proceeds at a different pace, which is bad. In manufacturing, for example, it takes months to add enough manufacturing capacity to meet a spike in demand. That means foundries will have to limit capacity for smaller customers.

While that makes good business sense from a foundry standpoint—TSMC’s annual report this year notes that its 10 largest customers accounted for 54% of sales—it has a ripple effect on design starts and EDA sales. TSMC’s report also showed that the number of fabless design starts actually dropped slightly in 2010, offset by an increase in chips designed by IDMs.

All of the major foundries are investing in new equipment to expand their fabs. But how quickly that capacity comes on line is hard to sync with increases in demand. And it gets even murkier once double patterning begins at 22nm, because that slows down the whole manufacturing process, and 2.5D stacking begins taking off, probably at the end of next year. Will the biggest customers still drive the volume, or will they produce pieces of designs that may be used as subsystems in a bigger stack? And will capacity that has been readily available for the biggest customers now be distributed among even smaller companies looking to package multiple chips in a package?

There is a lot of talk about the upside of all of this, but how it unfolds is unclear. The proof: Dozens of executives on all sides of the supply chain are all asking the same questions. They’re probably the right questions, too, but so far there are no clear answers.

–Ed Sperling

Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking.

Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers.

So what’s behind these move? In TI’s case, there appears to be a recognition that if analog can be put on a separate die then TI will be able to offer full subsystems or chips for specific vertical markets. When you think about it, that’s a lot more profitable than a team of engineers trying to retrofit analog functionality on 28nm or 22nm processes. Analog processes can survive for 10 years or more. Digital processes are turned over at the rate of Moore’s Law.

In the early part of the 00 decade, analog companies had largely given up on mixed signal processors because they were too hard to integrate. They changed their minds in the latter part of the decade as the smart phone revolution drummed up enough demand to warrant the investment. But the future appears to be a return to separate chips bound together by either a silicon interposer or through-silicon vias.

That makes analog designers far more important than they were a year ago, and it makes them far more valuable. TI hasn’t paid this much money for analog talent since it bought Burr-Brown in 2000 for $7.6 billion.

In Microsemi’s case, microwaves are becoming much more popular for advanced communications—particularly in the military space where terahertz clock frequencies are under development. At these kinds of speeds signal integrity is a challenge using standard RF technology.

What’s making these terahertz frequencies possible is a new metal-insulator-insulator-metal stack—a not-so-simple concept when you consider these designs suffer from some of the same kind of thermal issues as other stacked die. Putting two insulation layers together can create heat problems that require some sophisticated venting concepts.

We expect to see more consolidation in both of these spaces, and far more vertical solutions that can be quickly assembled with other die to reduce time to market significantly. While these are large sums of money, the acquisition frenzy appears to be just getting started.

–Ed Sperling

The old definition of a good chip was that it could be manufactured with reasonable yield, it was functionally solid, and it performed at least as well as the market demanded. That definition is changing, however.

There will always be a difference between ‘good’ and ‘good enough.’ We all want to own the ‘good’ chips in our electronic devices. But what’s noteworthy are the changes under way on the ‘good enough’ side and how they compare with the ‘good’ chips.

One change, of course, is the increased reliance on software. If the device isn’t life-critical and it can be fixed with a software patch—or if it’s a consumer device that will be replaced within a year or two—then a few glitches aren’t considered that important. The phone function still has to work on a smart phone, but it doesn’t necessarily have to work better than another phone. And the Internet access on a phone isn’t expected to be as good as a desktop connected via Ethernet.

A second change is that in some markets time to revenue is considered more important than great engineering. While advanced chip companies continue to invest in some of the best power-saving techniques for prolonging battery life, many OEMs that buy the chips and assemble them into final products don’t take advantage of those features. Or more accurately, they willfully ignore those features because it takes to long to optimize them.

Third, just having functionality is good enough in some markets even if it’s not the best implementations of those functions. As long as they work that’s considered good enough. The differentiator isn’t the technology. It’s the availability of new products. Even in the IP market, best of breed isn’t always as important as integrated and tested. The financial risk of getting it all wrong with all the best IP is huge when 70% or more of the chip is reusable or purchased IP. In fact, that’s potentially more costly than losing some market share to superior engineering.

There are pendulum swings in IC design, as there are in all markets. Companies that go for ‘good enough’ and that compete on price and time to market historically have run their course and been burned. What’s changed is that with complexity affecting even the best-run companies—witness Apple’s antenna problem, Intel’s Sandy Bridge chips and a long line of overheating batteries from multiple vendors—good enough isn’t always less reliable. In some cases, good enough may actually be better.

–Ed Sperling

The number of system-level design flaws is rising, and they’re not just little mistakes. These are high-profile errors that are making headlines all over the globe.

While it’s debatable whether Toyota’s problem was a hardware or software design glitch, the simple fact is there was a design flaw somewhere. That’s true for the BP Gulf of Mexico leak, regardless of who’s responsible for maintaining a drilling platform. And it’s no different for the Japanese nuclear plants, which were built too close together and designed with insufficient backup power.

Closer to home, Apple’s iPhone antenna design was flawed. So was Intel’s initial Sandy Bridge chip.

So what do all of these problems have in common? Engineers have long argued that they can engineer a solution for just about anything. They’re probably right, given the appropriate resources, an understanding of all possible scenarios and a well-defined set of conditions. But at the system level—and that includes everything from ICs to full-blown industrial facilities—rising complexity, time-to-market and cost pressures, and the inability of engineers to verify and predict everything that can go wrong in a given amount of time are causing everything from minor nuisances to full-blown disasters.

Looked at individually, these look like unrelated errors. Looked at together, however, they point to a much broader problem across the entire supply chain, from design to manufacturing. Things we have taken for granted, largely as a result of years of slow evolutionary tweaks, now require more radical reassessments. That includes everything from the tools being used to design and create systems to budgetary considerations about what can be cut and what areas need additional resources. Inside of many companies these kinds of decisions are highly politicized, and something clearly isn’t working.

This kind of reassessment needs to run end to end. If there’s a problem at the back end, chances are good that the initial design was flawed and that the people doing the design didn’t have the right kind of training. In the case of Apple and Intel, the problem wasn’t so much cost cutting as unbelievable complexity and aggressive schedules. Tools do exist to solve some of these problems, but it takes time to train people to use them and to understand their benefits—something verification engineers have been complaining about for the past decade.

Unfortunately, we will probably see more of these engineering mishaps in the future. It takes awhile for executives at public companies, who are used to living quarter by quarter, to recognize the full financial impact of not addressing these problems properly. This isn’t a new issue, either. The old adage of, ‘Penny wise, pound foolish,’ dates back to the mid-1600s.

But it’s also time for engineering teams to reassess what they do, how they verify it, and what’s considered good enough—and not good enough. While an antenna problem can be fixed with a case and improved in the next release, it’s a lot harder when the system is mission-critical and affects lives. Nevertheless, there are costs for both. Consumer trust takes years to build, but in the Internet era it can be destroyed in a matter of days.

Perhaps even more daunting, the cause of these problems can stem from outside of a company. A complex ecosystem of parts means that a company is only as good as its partners and its quality control procedures for third-party IP. If it doesn’t work right it’s the chipmaker’s problem. And in the case of fabless semiconductor companies, it might even be a glitch in the manufacturing process.

Getting all of this right starts with a great concept and a flawless design, but it doesn’t stop there. It’s now all about the system, and the definition of the system and what can go wrong inside that system are growing.

–Ed Sperling

Across the semiconductor industry—as well as many other end-product industries—there have been some well-documented and sober assessments of what impact the damage in Japan will have on business.

In the EDA business, these kinds of numbers will be much harder to determine. Japan is a big consumer of EDA tools for the leading-edge process nodes, but with disruptions in power it will be difficult for Japanese companies to keep their simulation and verification farms on schedule. That will cause a slowdown at the front end of the flow all the way back to the architectural modeling stage. How long that slowdown lasts ultimately will determine what tools these companies buy and when.

Most of these chipmakers have foreign offices, but transferring operations to those offices takes time. Even utilization of cloud-based infrastructures will take time. These are just being mapped out by major EDA companies. Ramp-up time will be measured in months, at best. Moreover, those kinds of shifts will require some significant attitude changes among chipmakers about sending proprietary data to an outside company—something they have been reluctant to do in the past.

Professional services to help with these kinds of very complex transitions also are likely to be in significant demand once Japanese companies regain their footing. The question is whether enough expertise can be provided by existing companies to bridge the gap until Japanese companies are back to normal, or whether those kinds of services will have to be augmented with additional skills, training and hiring, which will slow down the whole process.

For Japan, this is like running a competitive race with leg weights. The sheer magnitude of the devastation means that even the best-crafted disaster plans don’t suffice. That raises short-term questions about the effect on the overall Japanese chip industry, as well as long-term issues about what solutions it will choose. And that ripples back into the EDA world, where different scenarios are under discussion about how to best serve their Japanese partners—and how those partners are likely to fare. There are chipmakers in other regions of the globe, including South Korea, China, Taiwan, and even North America and Europe, that are running these scenarios, as well, trying to figure out just what this means to them.

There are no clear answers here, just as there are no clear answers inside of Japan about when the crisis will subside. But there certainly are a lot more questions being asked.

–Ed Sperling

It’s probably too harsh to say that multicore has been a failure, but it’s flat-out wrong to say it has been successful.

Multicore was an inevitable outgrowth of Moore’s Law. You simply can’t keep turning up the frequency for processors at advanced nodes without cooking the chip into oblivion. In theory, four cores running at a much cooler 1GHz should be better than one core running at 3GHz. By that thinking, 20 cores should be even better.

There are two main problems with that reasoning, however. First, most software isn’t suitable for parallel computing. Databases and embarrassingly parallel applications such as graphics and some scientific calculations work best. So do some of the EDA design tools. But the majority of applications that people use can’t be parsed out to more than a couple cores—generally two and no more than four—and they can’t be scaled as more cores are added to each new node.

Second, memory becomes a bottleneck when it’s shared by cores. The problem with using approaches such as virtualization across a multicore chip is that they’re all sharing a common memory. Even when memory is split up into multiple discrete segments, there is still a challenge to keep everything straight—and one that is hardly scalable for many more cores.

There are other issues, as well. Being able to quickly turn on and off cores requires at least some power to keep them operating. In addition, making all the cores the same size to handle any available application is an inefficient approach. A simple executable file doesn’t require as much energy for processing PowerPoint or Excel, but it may require more speed than e-mail.

The solution—and one that is gaining traction across the design world—is a different approach to using these cores. If the software applications cannot be written in parallel and written to scale, then why force the issue? The alternative is to design cores for specific applications or functions, each with its own block of memory—or at least with a wider I/O to reach that memory.

Wide I/O, whether it’s a transposer or a through-silicon via, is a major shift in thinking for how SoCs are designed. It’s not just about the I/O. It’s about the functioning of many parts of the chip, whether that’s a collection of processor cores in a single place or scattered around the SoC, and whether they’re the same or different. It’s also a recognition that the old approach of designing hardware as one-size fits all doesn’t benefit the application’s function, performance, or the amount of power that’s wasted in delivering that performance.

These are subtle changes in thinking, but the results will create a profound shift across hardware design for years to come.

–Ed Sperling

Selling EDA through a software-as-a-service model is hardly a new concept. It’s also not a particularly successful one. Despite some initial hype and sporadic attempts to revive it, the idea has fallen flat due to concerns about version control, security and an almost universal aversion to engineers having to send large files back and forth to a server.

The approach is getting a new look, however, although less from the software-leasing side and more from a cloud-based resources type of scheme. There are several things driving this change:

First, the sheer complexity of new designs has greatly bumped up the need for additional resources to complete these designs. Even the most advanced chip companies working in the wireless communications space are complaining that they don’t have enough resources to run simulation, synthesis and verification. Everything is already multithreaded and multiprocessing, and it’s still not enough processing power.

Second, that complexity is creeping into designs even back a couple of nodes on the Moore’s Law road map. The companies that were working at 180nm and 130nm are now dealing with designs at 90nm and 65nm. That has driven up the need for new tools, but the low margins on their designs are forcing them to consider alternatives to buying tools. This explains why companies like Altium and Physware are now offering cloud-based services, and why even the largest EDA players are starting to revisit this approach.

Third, the infusion of more software into chip design has further boosted the need for additional resources, particularly emulation boxes. Because software teams typically don’t have the budget for these kinds of machines they have been scheduling time when the hardware team isn’t using them. The problem is that the hardware teams now need more resources to handle more complex designs, which may force the combined teams to look for those resources elsewhere. Cloud is a logical extension.

3D stacking will only exacerbate the resources shortages when it begins hitting the market in late 2012 or 2013. At that point either there will be a boom in EDA tools sale or in EDA tools rentals, or both. And there may be a mad scramble to assemble the infrastructure as these changes unfold.

–Ed Sperling