For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm.

That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed off by one node the way strain engineering and immersion and double patterning have managed to rescue bulk CMOS and lithography, respectively, for several nodes.

Second, it means that the problems that have been averted at 22/20nm will be piled up with other problems that have been averted. For the most advanced chip developers working at the bleeding edge of Moore’s Law, this is not good news.

The unanswered question is just how much of the industry will be reeling from this bad news. Memory makers and Intel will certainly feel the pinch, and so will some of the high-volume smart-phone chipmakers, but if 3D stacking lives up to its promise the bigger issues may be well outside the physical layout and process world. They may be in areas such as IP integration, software development and integration, packaging, self test and correction, and verification.

The schism that is developing may no longer just be between the big and the small and the haves and the have nots. It may be between those with big physical problems, and those with virtual problems, and size may no longer be the key differentiator between a company that’s highly profitable and one that’s not, or between those able to wield the most leverage and those that can’t.

–Ed Sperling

It used to be easy to define a system. It was an ASIC, an ASSP or even an SoC. Increasingly, however, that definition isn’t nearly broad enough.

With power issues now spreading across an entire device and software being used to manage everything from embedded applications to board-level functionality, the system is now much bigger than a single chip or even a system in package. It now encompasses software, hardware, IP and firmware. And in the case of communications, it can reach even beyond the device itself.

This creates problems at the architectural, design and verification level. More has to be thought about up front, and it has to be able to be verified further downstream. But it also creates a huge opportunity for the EDA industry, which has been relatively flat for the past few years. Rather than just competing for a bigger piece of the same pie, the opportunity is to compete for a piece of a much bigger pie.

It also creates a new challenge, and some big questions that have yet to be answered. While hardware companies are accustomed to paying for EDA tools and IP, software companies are not. And in places like China, even FPGA tools are considered expensive so many lesser-quality freeware tools are in use by indigenous startups.

What isn’t known yet is who will actually gain control of this design and development process in the future. Will it be the hardware engineering managers, who can easily justify an investment in tools, or will it be the software engineering managers who are reluctant to spend? And will it happen in places like Taiwan, Europe and North America where tools are considered an effective alternative to expensive labor, or in places like China where time to market may be perceived as reliant on a large labor pool rather than better tools?

What is clear is there is money on the table for those companies come up with the right solution to bigger design challenges and which can price it accordingly for whichever segment comes out on top. But there are still a lot of unanswered questions about exactly what those challenges will be, who will be facing them and who will be paying for them.

–Ed Sperling

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process.

To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes mature and using standardized ASIC platforms becomes an option.

So far the answer isn’t clear, and it may not be the same for all fabless companies or at all stages of the 3D rollout. While IDMs will continue to develop most of the parts themselves, the big advantage of 3D is that fabless companies will be able to focus on what they do best and work around more standardized underpinnings. In planar chips that requires tweaking the base platform, which has made FPGA prototyping extremely popular. In 3D, that tweaking may be possible on a completely separate die and sometimes even in software, all of which will run atop a standard platform containing memory, a processor and the I/O.

This is a multi-year rollout, of course. The first chips from non-IDMs, which are expected to begin showing up in 2012, will likely be two layers. Those will be followed by three or more layers of silicon, all connected with through-silicon vias. During that time, ASIC platforms will become commoditized and standardized and FPGAs will have to follow the same route. In fact, it may be likely that FPGA prototyping will be replaced by FPGAs as part of the overall 3D structure if the programmable logic approach will succeed.

There is plenty of opportunity in this shift, and for EDA companies this may be the inflection point they have been waiting for. While they have had trouble competing with FPGA vendors, which subsidize their tools as part of the cost of the FPGA platform, the market for FPGA prototypes will likely remain flat or shrink as 3D stacking gains steam. And the complexity of 3D structures, complete with thermal and mechanical stress and power issues may dwarf the ability of layout tools that have become popular in FPGA floorplanning.

So far no one knows for sure what will happen in this market. But the writing is on the wall that change is coming, and in every change there are winners and losers. The only question is who’s going to be on which side.

–Ed Sperling

Prior to the Synopsys acquisition of Virage Logic, Synopsys seemed to have an almost exclusive relationship with ARM. Since then, Cadence and Mentor Graphics have both been cutting deals with ARM for support of its IP cores.

What’s changed? With regard to the Virage Logic acquisition, very little. Synopsys did acquire the ARC processor through that deal, but ARC had been much more focused on high-end audio and supplying all the necessary codecs that it decidedly was not a threat to ARM. And Synopsys and ARM continue to work closely together on a variety of fronts, both in ARM’s support of Synopsys’ standard IP for things like USB and Synopsys’ support of ARM’s processor IP.

But there has been far more activity between ARM and Synopsys’ top competitors of late. In September, Cadence rolled out an optimized implementation methodology for ARM’s new Cortex-A15 processor.  The two companies also created an ARM-Cadence Encounter reference methodology.  And this week, Mentor inked a deal for test and repair of ARM’s memories and processor cores.

So what gives? The answer may be less about competition between ARM and Synopsys than between ARM and Intel (and to a lesser extent Apple and MIPS). The two companies are about to embark on an all-out war in the tablet market and ARM is doing whatever it can to shore up the Cortex-A15 multicore processor as fast as it can. ARM’s big challenge has been performance, which it apparently has solved with the A15, while Intel’s big challenge is still power consumption. ARM has achieved its goal, and now Intel is racing to come up with a competitor, which it expects to introduce early next year.

While this is a new market for ARM, and potentially a massive opportunity, it’s unclear whether this is really a new market for Intel or one that potentially will cannibalize sales of notebook computers and netbooks. And ARM is wasting no time in marshaling whatever forces it can to roll out multiple generations of chips, IP and anything else necessary to win a piece of this new business.

–Ed Sperling

The use of more third-party IP inside SoCs coupled with problems encountered at advanced process nodes is turning up some interesting challenges—and pointing the industry in some interesting directions.

It’s a well-known fact that third-party IP isn’t always used as it was intended. Even internally developed IP isn’t always used as prescribed. It’s not unusual for chip developers to turn up the performance, turn down the power, or to introduce unanticipated noise around a piece of IP. This is all normal and part of designing a chip. Engineering managers grouse about the trouble with integrating IP, software and sometimes even the package, but in the end—at least until recently—it could all be fixed with some last minute tweaks—even after tapeout.

Companies are finding that isn’t always the case at 32/28nm, and at 22/20nm there will be even less leeway in repairing the damage. Moreover, there isn’t the kind of margin needed to provide extra padding for these kinds of potential problems. At advanced nodes, guard-banding boosts power beyond acceptable limits or reduces the overall performance of an SoC—or both.

What’s required at advanced nodes is a lot of give and take from all parts of the design team throughout the process. For companies that have design teams scattered around the globe, this presents a new problem. The days of labor arbitrage are ending. The system has to be tightly integrated, and parts need to be adjusted as the chip progresses at each stage by people who can address those issues in real time. That may mean tweaking everything from the RTL to the package, the software, and potentially even the board. For companies that have put teams in various time zones to keep development moving round the clock, this isn’t always possible.

At future nodes, it may even affect the entire ecosystem. For a disaggregated model to work with really complex designs the ecosystem has to function like a well-oiled machine. Scattering it across different time zones with language barriers doesn’t help. Scattering it across different disciplines, with their own language problems, doesn’t help either—particularly when those disciplines aren’t under the same engineering management. And while those problems may seem interesting on a passing note, they will become rather glaring as we move to advanced nodes and 3D stacking.

There has been a lot of talk about the advantages of IDMs and vertically integrated companies, but the real advantage probably has less to do with ownership than structured and open communication channels. The companies that figure out how to do that best will be the ones that will emerge as the next leaders in this industry. It appears that communication has suddenly become very important to system-level design. Unfortunately not everyone does it well, and fewer people do it well all the time and across multiple disciplines. It’s probably a good time to learn.

–Ed Sperling

For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high.

It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the best conductors of heat and removing the heat from the chip. It sounds odd, but early tests show this is working.

Clearly, nothing is ever as simple as it sounds in advanced semiconductor designs. There are still huge problems to work out in 3D with signal integrity, electrostatic discharge, TSV interconnects and automated tools and models. No one is sure how IP will react in this type of environment, and considering the amount of IP being used in a chip continues to grow understanding how it behaves in context is critical.

Nonetheless, there is at least one positive piece of information to emerge from all this about the biggest worry. And there’s nothing wrong with some good news every now and then.

–Ed Sperling

The big surprise at the GPU Technology Conference this year, spearheaded by Nvidia, isn’t that GPUs are getting faster or that they can do amazing things. It’s that so little attention has been paid to the volume platforms that people carry around in their pockets.

What has always been interesting about GPUs is they are the one platform where software can be truly parallelized and accelerated to take advantage of many cores and arrays of processors. For graphics-intensive applications—and there are some really interesting ones—the platform of choice is not the processor. It’s an array of many-core devices connected to a multicore processor.

This is a sizable market in its own right, of course. Modeling and simulation applications are the next big thing in medicine, oil exploration, scientific exploration, and molecular modeling. Drug companies, oil companies and universities pay big bucks for this kind of equipment. The more horsepower that can be connected to these applications to make them render images in multiple dimensions the better.

Consider, for example, Autodesk’s new 3ds Max program for interior designers and architects. It actually will follow the photons of light through glass, off shiny objects and create a photograph-accurate drawing within minutes using some very high-powered cloud-based GPUs. Or the Adobe 4D image processing that allows a camera to take photos using multiple (plenoptic) lenses, then reconstruct the image on the computer to focus near, far, or even create 3D pictures. Or the forthcoming ace pilot video game that uses 4 billion triangles to render realistic maps and flying in 3D.

This is cool stuff, for sure. Science and graphics have found their platform of choice, and there’s plenty of hard work underway in creating these kinds of simulations and models. It will probably even sell more workstations and computers, and in some cases run on back-end servers.

But for the real volume markets—the billions of portable multifunction devices—this is a long way from reality. Video eats power and creates heat. The software is still inefficient. And even cloud-based processing requires great graphical displays, which have to be plugged into the wall if they’re used for any length of time.

What’s intriguing about all of this is that while most markets have been converging, these two worlds are actually diverging. At some point there will have to be a bridge, but given the complexity of both worlds that may be far more difficult the longer these two worlds remain separate.

–Ed Sperling

The announcements out of ARM and Intel over the past couple week—and presumably from rivals AMD, MIPS and even Nvidia in coming weeks—are more than just a struggle for one-upmanship.

The goal is much more far-reaching and the stakes are significantly higher than who has the fastest processor or core or even the lowest-power version. In the past year there has been a massive push to expand ecosystems, cement relationships that are cross-industry, and to venture into adjacent markets as well as solidifying positions in existing markets.

These changes are the result of both economic and technology shifts. The convergence of functions into a single device, or at least a couple devices, is opening up markets on a scale that many companies never dreamed possible. Billions of smart phones can mean billions of chip sales. They also will mean a demand for better tools and ready-fit IP that works with both the gate-first and gate-last process technology at whatever power level is required.

For the design and IP industries, this is very good news in the short term. The demand for faster, smaller and cheaper will require some very complex tools because the problems to be solved are orders of magnitude more complex at each new node. At 22nm we likely will see new materials, new transistor structures, new power management techniques, new interface fabrics, and probably even new techniques for bonding and packaging multiple chips.

How all of this plays out in the long-term, however, remains to be seen. After a massive grab for market share, there ultimately will be some consolidation that reduce the number of market segments, the number of very expensive platform designs and ultimately the number of customers for all the tools and IP that will continue to be needed.

At that point there will be a battle to convince those shrinking number of customers that they need to pay top dollar for the value they’re receiving, because fewer customers gives the bargaining edge to the customer rather than the vendor. This is still a couple nodes off, but it may be time to start thinking about this—and possible adjacent markets that need exploring by both customers and tools vendors.

–Ed Sperling

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield.

What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no longer a sense of resignation that they won’t be partaking in the benefits of advanced nodes. In a 3D stacked die world, it doesn’t matter if the digital portion of the chip—particularly the memory and some of the logic and IP—are developed at 15nm or even 6nm. As long as the analog and some of the IP don’t have to follow the same process node progression, then it no longer matters. The rest is an integration exercise, and much of chip development these days is integration, anyway.

This is a fundamental shift for the industry as a whole, and it will require some significant planning at the system level. While it’s still possible to account for hot spots and signal integrity in a two-die structure, it becomes harder with each new layer. Place-and-route models have to include thermal dynamics, and they have to be built for multiple generations in the future so logic doesn’t sit on top of logic and cook the chip into oblivion. This can all done with some foresight and standardized approaches, of course. It’s what engineers are good at.

It also means more standardized interconnect models, most likely a network on chip type of approach, and better understanding of through-silicon vias and their effect on communication within the chip once they begin shrinking at future nodes. But what’s particularly interesting is that suddenly it brings everyone that abandoned Moore’s Law at 180nm back into the race. That means they will have no choice but to re-enter the market for advanced tools for everything from modeling to verification and software prototyping, and from layout to design for manufacturing.

Stacking die, for all its technological evolutionary roots, is a market discontinuity. And at every discontinuity in the industry there has been a scramble for market share, new tools and new customers. Let the race begin.

–Ed Sperling

There has always been a struggle between the verification and marketing sides of any chip company. The solution in the past has simply been to hire lots more verification engineers on a contract basis prior to tapeout and to muscle through the debug process.

Creating a more generic platform and differentiating it with software changes that equation, and that is raising lots of concern behind closed doors inside of EDA companies. It’s not that companies will use any fewer EDA tools to create those hardware platforms. It’s that time-to-market issues will supplant quality if the assumption is that software can be fixed later.

In the case of automobile companies, this will never happen. The trend will always be better hardware and software and more rigorous testing, even if it means sacrificing some features until the next year’s model is available. From a human standpoint, no error is acceptable. From a business standpoint, recalls are extremely expensive and errors can result in costly lawsuits and inflict permanent damage on a hard-earned corporate image.

But in the case of consumer electronics or even business technology, it’s more of an inconvenience to have to download a software patch than a tragedy. And in many cases, getting to market with a product that is functional and loaded with cool new features may be the best way to gain market share quickly—even if teams of software engineers have to work overtime to fix bugs after the product ships.

If Apple, which is known for getting products out the door with very few glitches, can make mistakes, then what about less-capable companies looking to take market share? Even with the glitch in the iPhone 4’s antenna, Apple continued to sell more devices because consumers are relatively accepting of bug fixes after purchase. And with most consumers trading up after a year or two, these are often considered temporary devices, anyway.

Still, what’s needed isn’t an acceptance that all products will be buggy in the future. It’s a way of solving these problems. Quality will always sell, and if quality controls can be automated and priced appropriately—the whole basis of semiconductor development and manufacturing—then it will sell more. Much more.

Rather than a problem for the semiconductor design market, this is a huge opportunity for EDA, and for both software and IP. Inconvenience in the vast consumer market is a problem spread out across lots of people in small increments. And where there is huge volume, there is a huge amount of money to be made.

–Ed Sperling