The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others.

The first significant shift is that SoCs are moving mainstream—and mainstream players are moving toward SoCs. Intel announced its intention to become a bigger SoC player several years ago at the Intel Developer Forum, and has begun offering foundry services in a modular approach to other companies building SoCs. That hasn’t amounted to much, so far. But add in a couple other pieces and the picture begins to change. eSilicon has been positioning itself to better control pieces of the supply chain and to document the behavior and characteristics of third-party IP to build complex SoCs. Now Open-Silicon is shifting its focus from ASICs to SoCs.

The big IP players have been busy finding a lucrative niche for themselves, too. Mentor Graphics, Synopsys and Cadence have made big investments in verification IP, as well as other IP they have been buying up and building for the past several years. And companies such as ARM, MIPS, Tensilica and Texas Instruments are battling for sockets in complex SoCs where one processor core is not enough and homogeneous cores aren’t the most efficient.

All of this stuff has to be integrated and connected, too, preferably in a coherent and flexible way. That helps explain the open hostilities between the two leading players in the network-on-chip arena—Sonics and Arteris—and the recent introduction by ARM of its Amba 4 Coherency Extensions (ACE). Connectivity is critical for this whole shift, and the opportunity is very large.

And on the foundry side, GlobalFoundries and TSMC, have been developing developed interposer technology, adding DFM and DFY support for complex SoCs, and slowly building expertise on full 3D integration, which they expect to begin rolling out en masse over the next couple of years.

Each of these moves position these players, as well as startups in places such as China and India, for packaging and stacking of die, the emergence of complex pre-verified subsystems that can be assembled more quickly and cheaply than in the past, and for new services along the way to help create and integrate SoCs. While ASIC design starts have remained flat, the number of design starts for complex subsystems that will be every bit as complex as an ASIC will increase dramatically. That, in turn, will reshape what tools are needed, how they’re sold, and how companies go to market.

Taken in isolation, none of these moves amounts to much more than noise. Over the years there has been plenty of noise, making it hard to decipher real movement from marketing hype. And in a disaggregated industry, moves by one company have to be synchronized with others to be significant. But looked at together, it’s becoming clear that the entire IC ecosystem is in motion and jockeying for change. From here on, things should get quite interesting.

–Ed Sperling

The basic rule of SoC design is that it needs to be created relatively quickly, work as planned, and that it can be manufactured at a reasonable cost and with good yield ramp. That eliminates revolutionary changes on the technology side, limits the number of new materials, and relegates the most dramatic shifts to the business.

That’s why most of the most far-reaching technology research is being done by universities rather than companies these days, and it’s why most of the stuff being proposed has been in the works for at least a decade or more. Through-silicon vias have been around for years, even though the fine details of how to drill them into CMOS or SOI with minimal impact is still being worked out. But some of the other pieces in 3D are already being used commercially by MEMS makers. And in the case of 2.5D stacking, that approach dates back to the early 1990s with system-in-package and multi-chip modules.

The business side is another matter entirely, and it will drive new technology like never before. This is where the radical changes will come into play, mostly because partnerships will have to be much more tightly integrated so that the supply chain can work as a single entity. That will require someone to take on the role of general contractor, and it’s uncertain whether that will involve a single type of company or whether that role will be more fluid. But one thing is for certain: There will be a struggle to see who can take the biggest share of the pie.

This ultimately will cause a shakeout are various points along the line, too, as companies figure out the next steps. That most likely will involve acquisitions, as struggling companies seek to cash in on a sure thing and larger companies look to gain a foothold more quickly than they could through organic growth. But it also will involve some interesting business arrangements between strong companies, no matter what their size, that can leverage either unique technology and market position and which ultimately will have no choice but to contract the number of companies with which they are working.

At that point, the next wave of competition will begin in earnest, with the goal of getting to market fastest, cheapest and with the most compelling or customized offering for particular vertical markets. If this was a sports competition, we’d now be in the planning stage of the qualifying matches, which will unfold over the next few years. After that, things should get very interesting.

–Ed Sperling

The move to stacked die poses some interesting technology challenges and promises significant technology benefits, but the real driver is business—and for this market to work, it has to continue being about business.

In the past it was technology first, business last. We are now at the stage where it is business first, technology last. Re-use of entire die as subystems, better use of design resources, predictable yields on older technologies and the ability to not have to re-design analog or standard IP at advanced nodes can provide enormous dollar savings to developers.

That doesn’t mean that technology gets left in the dust, of course. Wide I/O and shorter wires, rationalization of how memory gets used, connecting cores directly to memory bits and matching the needs of specific applications with right-sized processors are all important advances in SoC design. Performance can be boosted significantly, power can be cut and best-of-breed IP can be developed or purchased to make these chips even better.

But all of this has to be weighed against cost—including hidden costs such as time to market and fuzzy costs such as yield. The real formula to consider here is time to profitability and that will depend on a number of factors. Interposers in 2.5D stacks, or TSVs in true 3D stacks, need to be perfected and commoditized. Drilling through a thinner piece of silicon isn’t simple stuff. Understanding the impact on physical stress is still incomplete, and none of this has been done over time.

In addition, packaging needs to be competitive with existing packages—if not exactly in price, then at least close enough. Time to market with sufficient yields needs to be proven. Full characterization of IP and subsystems needs to be completed for a variety of implementations—particularly in stacks—to avoid nasty physical effects. And IP vendors need to make the necessary investment to make this happen. Moreover, standards need to be developed, particularly in areas such as layout and business responsibility and liability to make sure this all goes smoothly.

None of this will happen overnight, and some of it may be a chicken-and-egg decision where companies hold back on their investment until they see others taking steps in this direction. Market timing, yet another business element, is very important. But if the business of technology is to move forward, the business itself will have to make some important commitments. And in this case, time is of the essence.

–Ed Sperling

Talking about stacked die is sort of like describing Africa as a country. First of all, it’s wrong—despite some politicians’ statements to the contrary. And second, lumping everything together under a single heading probably adds more confusion than clarity.

There are several ways to approach this semantics problem. One is by function. Memory on memory, memory on logic, and logic on logic are meaningful ways of looking at stacked die. Each says something different about how chips are being organized, and each gives an indication of the problem being solved and potential issues that may arise. In the first two the challenges will be focused mostly on bandwidth and accessibility. In logic-on-logic implementations the technical challenges will largely be relegated to physical effects such as heat dissipation, expansion coefficients and signal integrity.

A second tack is to break it down by packaging approaches, and there are a bunch of these. System-in-package and multichip module are different from a 2.5D stack using an interposer. But when you consider Xilinx’s four-tile 2D structure connected by an interposer, is that a horizontal stack? And what exactly is real 3D? Is it simply adding through-silicon vias, or does it require logic on logic?

A third way of looking at this is from the standpoint of markets while ignoring the underlying architecture. Is it a MEMS chip, a logic chip, cell phone SoC? And what happens when you ignore the changes that will be forced upon many parts of the ecosystem by combining various functions in different layers.

The problem, of course, is that none of these lines will remain clear. Combinations of technology—a 3D memory on top of a 2.5D logic chip, for example—eliminates any chance of a clear-cut description about exactly what is being designed. Adding more functionality into chips makes it hard to describe what exactly they do. And mixing older generations of technology with newer ones will even make it hard to describe whether a chip is new, old, or somewhere in between.

But this needs to be viewed as more than just an idle intellectual exercise. Companies have come and gone because they couldn’t easily describe their technology, despite the fact that it was unique and valuable to potential customers. Stacking die is a big step forward technically, but there also needs to be clarity in how to describe the various stacking approaches. Without it, we may create one of the worst marketing nightmares the semiconductor industry has ever seen.

–Ed Sperling

The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the charge.

This is the first of several major shifts that will begin over the next few process nodes. One will involve lithography, where double patterning and computational scaling will become more prevalent starting at 22nm. The second involves the proliferation of lots more 3D structures on wafers, including everything from multi-gate transistors such as Intel’s tri-gate FinFETs to MEMS devices and 3D memory. A third involves stacking of die, which is expected to bridge multiple process nodes together initially, with more complete modeling and the proliferation of through-silicon vias over time.

What’s becoming clear is that we’ve just scratched the surface when it comes to power and performance. Wide I/O, right-sized processor cores, more efficient software, co-development of hardware and software and better connectivity externally and internally will provide significant boosts in performance while also cutting power consumption. There are huge gains to be made over the next couple nodes in both areas.

What few people are talking about, however, are the physical effects that need to be considered in developing this new breed of chips. Time-to-market pressures will force much more re-use, more concurrent design and more experimentation with new ways of making that happen faster. But in the rush to get chips out the door, there will be all sorts of new challenges to deal with. How do EMI and ESD change in a chip that is densely packed with FinFETs, for example? How do vertical stacks and vertical structures affect noise-sensitive analog IP? And what happens when you start mixing firmware, software and hardware with third-party IP? How does all of this affect timing closure? And what sort of impact will there be from turning on and off segments of a chip that may include lots of 3D structures in a 3D stack?

We have come a long way in verifying the functional aspects of SoCs. The next big challenge will be understanding the physical effects and how to model them effectively. The introduction of FinFETs is a major step forward, but we still have a long way to go to really understand how all the pieces fit together.

–Ed Sperling

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent.

To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC, this represents a huge shift—and opportunity. It’s an entry point into the fast lane that previously was dominated by ASICs, with performance and power overhead muted by shorter distances and wide I/O connections to memory chips.

For EDA vendors, the real upside of 3D is around the edges of the technology, and in the potential that new customers will require new tools. Mentor’s push into 3D test is a case in point. Cadence’s integration push will likely fit into this scenario, as well. And the push by Synopsys deeper into the IP world will likely find new growth potential in 3D. There’s also an opportunity for exploring everything from thermal impacts of different IP to 3D topographical layout tools. But the real hope in EDA is that when companies begin putting together 2.5D and 3D packages based on pre-integrated blocks of IP, or possibly even fully integrated die, that complexity will drive customers to start buying more advanced tools.

For the supply chain as a whole, 3D offers a new challenge. It’s a matter of working with partners more closely than in the past—possibly new partners—to deal with more choices and significantly more complexity. This is easier said than done, because understanding a partner’s real strengths won’t be apparent until stacking die becomes a more mature solution. There are risks inherent in any partnership, and there are costs of going to market even with the right partners. But with stacked configurations, those costs are multiples of what they might be in 2D layouts.

–Ed Sperling

Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking.

Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers.

So what’s behind these move? In TI’s case, there appears to be a recognition that if analog can be put on a separate die then TI will be able to offer full subsystems or chips for specific vertical markets. When you think about it, that’s a lot more profitable than a team of engineers trying to retrofit analog functionality on 28nm or 22nm processes. Analog processes can survive for 10 years or more. Digital processes are turned over at the rate of Moore’s Law.

In the early part of the 00 decade, analog companies had largely given up on mixed signal processors because they were too hard to integrate. They changed their minds in the latter part of the decade as the smart phone revolution drummed up enough demand to warrant the investment. But the future appears to be a return to separate chips bound together by either a silicon interposer or through-silicon vias.

That makes analog designers far more important than they were a year ago, and it makes them far more valuable. TI hasn’t paid this much money for analog talent since it bought Burr-Brown in 2000 for $7.6 billion.

In Microsemi’s case, microwaves are becoming much more popular for advanced communications—particularly in the military space where terahertz clock frequencies are under development. At these kinds of speeds signal integrity is a challenge using standard RF technology.

What’s making these terahertz frequencies possible is a new metal-insulator-insulator-metal stack—a not-so-simple concept when you consider these designs suffer from some of the same kind of thermal issues as other stacked die. Putting two insulation layers together can create heat problems that require some sophisticated venting concepts.

We expect to see more consolidation in both of these spaces, and far more vertical solutions that can be quickly assembled with other die to reduce time to market significantly. While these are large sums of money, the acquisition frenzy appears to be just getting started.

–Ed Sperling

For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high.

It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the best conductors of heat and removing the heat from the chip. It sounds odd, but early tests show this is working.

Clearly, nothing is ever as simple as it sounds in advanced semiconductor designs. There are still huge problems to work out in 3D with signal integrity, electrostatic discharge, TSV interconnects and automated tools and models. No one is sure how IP will react in this type of environment, and considering the amount of IP being used in a chip continues to grow understanding how it behaves in context is critical.

Nonetheless, there is at least one positive piece of information to emerge from all this about the biggest worry. And there’s nothing wrong with some good news every now and then.

–Ed Sperling

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield.

What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no longer a sense of resignation that they won’t be partaking in the benefits of advanced nodes. In a 3D stacked die world, it doesn’t matter if the digital portion of the chip—particularly the memory and some of the logic and IP—are developed at 15nm or even 6nm. As long as the analog and some of the IP don’t have to follow the same process node progression, then it no longer matters. The rest is an integration exercise, and much of chip development these days is integration, anyway.

This is a fundamental shift for the industry as a whole, and it will require some significant planning at the system level. While it’s still possible to account for hot spots and signal integrity in a two-die structure, it becomes harder with each new layer. Place-and-route models have to include thermal dynamics, and they have to be built for multiple generations in the future so logic doesn’t sit on top of logic and cook the chip into oblivion. This can all done with some foresight and standardized approaches, of course. It’s what engineers are good at.

It also means more standardized interconnect models, most likely a network on chip type of approach, and better understanding of through-silicon vias and their effect on communication within the chip once they begin shrinking at future nodes. But what’s particularly interesting is that suddenly it brings everyone that abandoned Moore’s Law at 180nm back into the race. That means they will have no choice but to re-enter the market for advanced tools for everything from modeling to verification and software prototyping, and from layout to design for manufacturing.

Stacking die, for all its technological evolutionary roots, is a market discontinuity. And at every discontinuity in the industry there has been a scramble for market share, new tools and new customers. Let the race begin.

–Ed Sperling

There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump.

Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chips that used to be in a package is a lot different than designing a chip where the logic may be spread across two or more die that are bonded together. And putting memory on top of a processor and calling a 3D chip is not the same as optimizing the chip for performance, power and understanding the thermal implications of putting one block on top of another.

On the flip side, everyone is talking about the same direction. It’s just a question of where they sit on that evolution from system-in-package to a true 3D layout and synthesis. Memory makers are already building 3D configurations, and some of the most advanced chipmakers are already working on 3D chips they’re not willing to talk about just yet.

The next step is to commercialize this process beyond just a few, which is where EDA tools come in. The companies that can bridge the gap between the most advanced digital processes and lagging analog processes stand to profit handsomely because they will be acting as a bridge between the economic necessity of some companies to push forward to the next node and the economic pain that kind of approach is causing other companies.

There is much work to be done in this area, of course. Modeling in 3D doesn’t exist today. Through-silicon vias are still a work in progress. Secondary problems such as electrostatic discharge, electromigration and parasitics need to be dealt with. Thermal issues need to be dealt with at the architectural stage. And standards have to be developed across the board.

But none of these is new. What is new is the prospect of unifying both ends of the semiconductor spectrum in SoCs that can both improve performance and use less power, which can use the manufacturing process that makes sense for a particular technology, and which can re-use vast amounts of previous chips to lower the overall cost of development.

In semiconductor design, 3D stacking is an enormous opportunity. The only question now is who will get there first.