The recent pushes by both Synopsys and Mentor into new markets should say something about the state of EDA. Being able to lay out the wires and subsystems on a chip, not to mention verifying that it all works, will always be vital to getting SoCs to tapeout. But that kind of work will not generate the kind of growth the big EDA companies are looking for—at least not without some major tweaks to their business models.

Mentor’s purchase of Valor is a case in point. Valor’s expertise is at the board level. But with system-level design now stretching well beyond the chip to include everything from high-speed interconnects between multiple chips on a board, to power savings at every level, that’s beginning to make far more sense. It’s still impossible to simulate an entire system—in this case, system extends well beyond the boundaries of the silicon—but the industry is clearly heading in that direction. It will always be essential to verify and synthesize blocks, but it also will be necessary to step up to a much higher level of abstraction and consider how all the pieces in an end device go together.

Synopsys has been working this from a different angle, as evidenced by the recent purchases of CoWare and VaST. Software is another key piece in this puzzle, and prototyping software early enough in the design and with enough accuracy to make it useful has become a really thorny problem in systems development. The challenge in Synopsys’ case may be less about the tools it creates than the ability of chipmakers to effectively use them. Being able to bridge hardware and software and co-develop them in tandem—meaning if the software has to be tweaked, the hardware team responds with their own tweak, and vice versa—isn’t something most companies have experience with.

While large chipmakers continue to generate complex chips, other chip makers are either focused on FPGA prototypes, FPGAs in end products, or looking at ways to use platform-based designs. The FPGA business is growing, particularly in places like China, where most of that growth is occurring with the tools provided by FPGA vendors. Adding in analog programming, as Actel has done, or adding programmability into SoCs, as companies like Intel have done, are basically flip sides of the same concept. A good portion of the challenge is in the integration of various pieces, and the more flexibility that can be added into the chip’s engineering the easier it is to fix if problems do occur or changes are needed at the last minute.

That’s also why more IP is now being sold in pre-integrated blocks. Grandiose predictions about of thousands of independent IP makers around the globe never materialized, but the potential for discrete pieces of IP that can connect to other IP platforms is very real. The fact that foundries are now verifying IP from companies like Virage Logic—which bought ARC at least partly for this reason—as well as standard IP from Synopsys and ARM speaks volumes about the direction of things to come. It’s no longer just about the chip. It’s how all the pieces in a device go together, starting at the most basic level and extending out to the end-user applications. Fortunately for RTL and systems engineers, no one understands how to put the pieces together better than the people who can create the silicon to drive it all.

—Ed Sperling

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single chip takes the place of multiple chips and the number of components on a board shrinks dramatically.

The next phase, and we’re just beginning to witness this, is combining pieces that normally don’t go together very well. This has been true for several years at the bleeding edge of the SoC world, where companies like Broadcom and Qualcomm have been building more analog onto chips. It’s now beginning to invade the more mainstream chip world, such as industrial and medical electronics. Actel’s move to combine programmable analog with an ARM microcontroller subsystem is a case in point.

What is less clear is who ultimately will reap the benefit of all the incredibly difficult integration work that needs to be done to make all these parts work together. Clearly this is the hardest stuff, and it’s something most engineering teams are reluctant to get involved with. It’s the same rationale behind buying multiple blocks of integrated IP rather than single blocks and doing the integration yourself, which has played out well for companies like Virage Logic, Synopsys and Mentor Graphics.

Despite analyst predictions that independent IP vendors would disaggregate the market, the trend has gone the other way. It’s not that small IP development teams don’t produce great IP. It’s that the integration of that IP with other IP blocks and manufacturing processes is a lot more difficult than creating a single IP block.

From a business standpoint, this is a reflection of a new direction of consolidation. As markets shrink, consolidation occurs. But what has changed, rather suddenly and somewhat subtly, is the reason for this consolidation. It’s not based upon lack of business. It’s based upon complexity and the interaction of many pieces from multiple vendors. Moreover, rather than being confined to the edge of Moore’s Law, the problems felt at the most advanced geometries are now pervasive.

This is an interesting shift, and it should produce some interesting solutions over the next few years—not to mention some business upsets in unexpected places.