The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the charge.

This is the first of several major shifts that will begin over the next few process nodes. One will involve lithography, where double patterning and computational scaling will become more prevalent starting at 22nm. The second involves the proliferation of lots more 3D structures on wafers, including everything from multi-gate transistors such as Intel’s tri-gate FinFETs to MEMS devices and 3D memory. A third involves stacking of die, which is expected to bridge multiple process nodes together initially, with more complete modeling and the proliferation of through-silicon vias over time.

What’s becoming clear is that we’ve just scratched the surface when it comes to power and performance. Wide I/O, right-sized processor cores, more efficient software, co-development of hardware and software and better connectivity externally and internally will provide significant boosts in performance while also cutting power consumption. There are huge gains to be made over the next couple nodes in both areas.

What few people are talking about, however, are the physical effects that need to be considered in developing this new breed of chips. Time-to-market pressures will force much more re-use, more concurrent design and more experimentation with new ways of making that happen faster. But in the rush to get chips out the door, there will be all sorts of new challenges to deal with. How do EMI and ESD change in a chip that is densely packed with FinFETs, for example? How do vertical stacks and vertical structures affect noise-sensitive analog IP? And what happens when you start mixing firmware, software and hardware with third-party IP? How does all of this affect timing closure? And what sort of impact will there be from turning on and off segments of a chip that may include lots of 3D structures in a 3D stack?

We have come a long way in verifying the functional aspects of SoCs. The next big challenge will be understanding the physical effects and how to model them effectively. The introduction of FinFETs is a major step forward, but we still have a long way to go to really understand how all the pieces fit together.

–Ed Sperling

The wall is in sight.

Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid down well beyond that.

But at 22nm—or the half node of 20nm—things seem to get a bit fuzzier than in the past. You can’t just fix one problem anymore. You have to fix a bunch of them simultaneously. And those problems become thornier as you progress down to 10nm. Even the fastest ASICs and processors will begin to look more like systems designs than chips, and designs will expand well beyond the physical limits of the silicon to include software, other components on a board and the manufacturing processes to create them.

This used to be so far in the future that no one really gave it much thought. It was something you talked about over a beer. But with companies now working on 32 nanometer IP blocks and manufacturing processes, it won’t be that long before we start seeing the wall. There will be ways around the wall, of course, but the path will hardly be a straight line.

At the very basic level, lithography technology will have to change. The move to extreme ultraviolet lithography has been talked about for years. TSMC already has committed publicly to immersion lithography. But which way the industry ultimately heads is the subject of lots of research at the moment. So far, there are no clear answers. Both technologies are subject to defects, and while those defects may not be significant at 180nm, they will ruin a chip at 20nm.

On top of that, new transistor designs will be needed. Chip designs already have started going vertical. Memory makers are using stacked die to create their chips. But we’re also starting to see the need for new transistor designs such as FinFETS, which have 3D fins resembling a 1958 Cadillac.

Add to that such technologies as air gap, new materials and substrates such as silicon-on-insulator, and suddenly the wall begins to take shape. From a distance it looks opaque, but up close it’s porous. The only problem is that getting through it requires a huge investment in new technology.

Moore’s Law originally was created as an economic statement of manufacturing economies of scale. The further down the road map, the more the economies of scale begin rolling out in reverse. Many companies have been wondering where the tipping point will be for Moore’s Law, and it varies by company. But the end of the road may be when the last company no longer gets a benefit from putting more transistors on a piece of silicon—no matter what shape they take or how exotic the substrate.

–Ed Sperling