The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield.

What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no longer a sense of resignation that they won’t be partaking in the benefits of advanced nodes. In a 3D stacked die world, it doesn’t matter if the digital portion of the chip—particularly the memory and some of the logic and IP—are developed at 15nm or even 6nm. As long as the analog and some of the IP don’t have to follow the same process node progression, then it no longer matters. The rest is an integration exercise, and much of chip development these days is integration, anyway.

This is a fundamental shift for the industry as a whole, and it will require some significant planning at the system level. While it’s still possible to account for hot spots and signal integrity in a two-die structure, it becomes harder with each new layer. Place-and-route models have to include thermal dynamics, and they have to be built for multiple generations in the future so logic doesn’t sit on top of logic and cook the chip into oblivion. This can all done with some foresight and standardized approaches, of course. It’s what engineers are good at.

It also means more standardized interconnect models, most likely a network on chip type of approach, and better understanding of through-silicon vias and their effect on communication within the chip once they begin shrinking at future nodes. But what’s particularly interesting is that suddenly it brings everyone that abandoned Moore’s Law at 180nm back into the race. That means they will have no choice but to re-enter the market for advanced tools for everything from modeling to verification and software prototyping, and from layout to design for manufacturing.

Stacking die, for all its technological evolutionary roots, is a market discontinuity. And at every discontinuity in the industry there has been a scramble for market share, new tools and new customers. Let the race begin.

–Ed Sperling

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs.

It also has been revised on more than one occasion as the time frame in which the number of transistors doubles has floated between 18 and 24 months. And it has been predicted to die on multiple occasions, starting back at 1 micron (aka 1,000nm) when lithography was believed to be at its physical limit.

Moore’s Law has defied all predictions and all odds. Some companies have jumped off the bandwagon and moved in different directions, while the largest continue to adhere to its advancement with almost religious fervor. But the real future of Moore’s Law be less of a mark of size of the company making the investment in a new chip than a piece of an overall system that limits the use of advanced process nodes for extremely regular structures in places where space matters but little else.

As we move into 3D stacking over the next few years and tighter integration between software and system design, the real future of Moore’s Law may be less impact on the overall system and less importance for what makes one chip different from another. Rather than come to an abrupt end, Moore’s Law may be the part of the chip that is most commoditized rather than the part that wields the competitive edge.

This is a rather shocking end game for a formula that has dictated how chips were developed throughout most of the history of ICs. But it also means that companies will need to start looking beyond Moore’s Law and replacing it with new formulas, approaches and structures—ones that may have far less impact over the long haul but which will be just as important for the generation of semiconductors that benefit from them. The same variables of area, power and performance still matter, but they will no longer be defined by the line width between all the components on a chip.

–Ed Sperling

The wall is in sight.

Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid down well beyond that.

But at 22nm—or the half node of 20nm—things seem to get a bit fuzzier than in the past. You can’t just fix one problem anymore. You have to fix a bunch of them simultaneously. And those problems become thornier as you progress down to 10nm. Even the fastest ASICs and processors will begin to look more like systems designs than chips, and designs will expand well beyond the physical limits of the silicon to include software, other components on a board and the manufacturing processes to create them.

This used to be so far in the future that no one really gave it much thought. It was something you talked about over a beer. But with companies now working on 32 nanometer IP blocks and manufacturing processes, it won’t be that long before we start seeing the wall. There will be ways around the wall, of course, but the path will hardly be a straight line.

At the very basic level, lithography technology will have to change. The move to extreme ultraviolet lithography has been talked about for years. TSMC already has committed publicly to immersion lithography. But which way the industry ultimately heads is the subject of lots of research at the moment. So far, there are no clear answers. Both technologies are subject to defects, and while those defects may not be significant at 180nm, they will ruin a chip at 20nm.

On top of that, new transistor designs will be needed. Chip designs already have started going vertical. Memory makers are using stacked die to create their chips. But we’re also starting to see the need for new transistor designs such as FinFETS, which have 3D fins resembling a 1958 Cadillac.

Add to that such technologies as air gap, new materials and substrates such as silicon-on-insulator, and suddenly the wall begins to take shape. From a distance it looks opaque, but up close it’s porous. The only problem is that getting through it requires a huge investment in new technology.

Moore’s Law originally was created as an economic statement of manufacturing economies of scale. The further down the road map, the more the economies of scale begin rolling out in reverse. Many companies have been wondering where the tipping point will be for Moore’s Law, and it varies by company. But the end of the road may be when the last company no longer gets a benefit from putting more transistors on a piece of silicon—no matter what shape they take or how exotic the substrate.

–Ed Sperling