What we’re witnessing isn’t just the return to a collection of chips on a board that were put there because they couldn’t be incorporated into the main logic chip. Instead, this is a well-thought-out, extremely granular approach to what goes where. In many cases, it will be cost that drives these decisions. But at least part of the business decision will be an understanding of how to get processing done the most effectively and with the least amount of energy. In essence, you only add what you need.

Think about a smart phone, for example. The key challenge there is battery life, not performance. If you don’t plug it in at night, or you run applications with lots of graphics, your phone begins showing the red bar of death. Continue using it at your own peril. In this type of setting, the market has been almost exclusively ARM- or MIPS-based. In the future, it could well be based on multiple chips, including Intel-based SoCs, as more performance is added into these devices to make them more useful.

This trend is particularly evident in tablet devices such as the iPad, where streaming video processing is required and where search needs to be sufficiently fast, but where battery life also needs to be sufficient to last through a long user session. In this case both performance and energy efficiency are required, often at a very granular level depending upon user preferences. Instead of an ARM or MIPS processor for efficiency, the ARM or MIPS processors may be the main performers, coupled with an ARC processor or Tensilica DSP for audio and an Intel processor for efficient search.

The semiconductor industry historically has used general-purpose processors with customized software and IP. In the future, designs likely will entail a combination of much more tailored processors that more effectively use even more tailored software and IP. And as simple as this sounds in theory, the impact will be enormous for everyone involved—from design to verification to manufacturing to the end users of the devices.

–Ed Sperling

What’s changed? With regard to the Virage Logic acquisition, very little. Synopsys did acquire the ARC processor through that deal, but ARC had been much more focused on high-end audio and supplying all the necessary codecs that it decidedly was not a threat to ARM. And Synopsys and ARM continue to work closely together on a variety of fronts, both in ARM’s support of Synopsys’ standard IP for things like USB and Synopsys’ support of ARM’s processor IP.

But there has been far more activity between ARM and Synopsys’ top competitors of late. In September, Cadence rolled out an optimized implementation methodology for ARM’s new Cortex-A15 processor.  The two companies also created an ARM-Cadence Encounter reference methodology.  And this week, Mentor inked a deal for test and repair of ARM’s memories and processor cores.

So what gives? The answer may be less about competition between ARM and Synopsys than between ARM and Intel (and to a lesser extent Apple and MIPS). The two companies are about to embark on an all-out war in the tablet market and ARM is doing whatever it can to shore up the Cortex-A15 multicore processor as fast as it can. ARM’s big challenge has been performance, which it apparently has solved with the A15, while Intel’s big challenge is still power consumption. ARM has achieved its goal, and now Intel is racing to come up with a competitor, which it expects to introduce early next year.

While this is a new market for ARM, and potentially a massive opportunity, it’s unclear whether this is really a new market for Intel or one that potentially will cannibalize sales of notebook computers and netbooks. And ARM is wasting no time in marshaling whatever forces it can to roll out multiple generations of chips, IP and anything else necessary to win a piece of this new business.

–Ed Sperling

It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of the design.

There is more pressure to do more up front than ever before. There also is more pressure for EDA vendors of all sizes to find unique growth markets that extend beyond the latest process node on the Moore’s Law road map. While there will still be some components that have to be made at the latest process node, there will be many others that do not—particularly as new techniques of building chips such as 3D stacking or systems-in-package with much faster interconnects and networking schemes begin rolling out.

This has set off a positioning scramble the likes of which hasn’t been seen since EDA was a nascent market. As large companies begin reaching out in new directions—Cadence with software and IP, Synopsys with software prototyping and Mentor with board-level design—as well as continued expansion by the IP vendors, we’re about to witness some fundamental shifts that can only be characterized as good.

The mantra among many EDA industry executives is that necessity is the mother of invention. There is plenty of necessity, and right now we’re witnessing the invention.

–Ed Sperling

The recent pushes by both Synopsys and Mentor into new markets should say something about the state of EDA. Being able to lay out the wires and subsystems on a chip, not to mention verifying that it all works, will always be vital to getting SoCs to tapeout. But that kind of work will not generate the kind of growth the big EDA companies are looking for—at least not without some major tweaks to their business models.

Mentor’s purchase of Valor is a case in point. Valor’s expertise is at the board level. But with system-level design now stretching well beyond the chip to include everything from high-speed interconnects between multiple chips on a board, to power savings at every level, that’s beginning to make far more sense. It’s still impossible to simulate an entire system—in this case, system extends well beyond the boundaries of the silicon—but the industry is clearly heading in that direction. It will always be essential to verify and synthesize blocks, but it also will be necessary to step up to a much higher level of abstraction and consider how all the pieces in an end device go together.

Synopsys has been working this from a different angle, as evidenced by the recent purchases of CoWare and VaST. Software is another key piece in this puzzle, and prototyping software early enough in the design and with enough accuracy to make it useful has become a really thorny problem in systems development. The challenge in Synopsys’ case may be less about the tools it creates than the ability of chipmakers to effectively use them. Being able to bridge hardware and software and co-develop them in tandem—meaning if the software has to be tweaked, the hardware team responds with their own tweak, and vice versa—isn’t something most companies have experience with.

While large chipmakers continue to generate complex chips, other chip makers are either focused on FPGA prototypes, FPGAs in end products, or looking at ways to use platform-based designs. The FPGA business is growing, particularly in places like China, where most of that growth is occurring with the tools provided by FPGA vendors. Adding in analog programming, as Actel has done, or adding programmability into SoCs, as companies like Intel have done, are basically flip sides of the same concept. A good portion of the challenge is in the integration of various pieces, and the more flexibility that can be added into the chip’s engineering the easier it is to fix if problems do occur or changes are needed at the last minute.

That’s also why more IP is now being sold in pre-integrated blocks. Grandiose predictions about of thousands of independent IP makers around the globe never materialized, but the potential for discrete pieces of IP that can connect to other IP platforms is very real. The fact that foundries are now verifying IP from companies like Virage Logic—which bought ARC at least partly for this reason—as well as standard IP from Synopsys and ARM speaks volumes about the direction of things to come. It’s no longer just about the chip. It’s how all the pieces in a device go together, starting at the most basic level and extending out to the end-user applications. Fortunately for RTL and systems engineers, no one understands how to put the pieces together better than the people who can create the silicon to drive it all.

—Ed Sperling

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single chip takes the place of multiple chips and the number of components on a board shrinks dramatically.

The next phase, and we’re just beginning to witness this, is combining pieces that normally don’t go together very well. This has been true for several years at the bleeding edge of the SoC world, where companies like Broadcom and Qualcomm have been building more analog onto chips. It’s now beginning to invade the more mainstream chip world, such as industrial and medical electronics. Actel’s move to combine programmable analog with an ARM microcontroller subsystem is a case in point.

What is less clear is who ultimately will reap the benefit of all the incredibly difficult integration work that needs to be done to make all these parts work together. Clearly this is the hardest stuff, and it’s something most engineering teams are reluctant to get involved with. It’s the same rationale behind buying multiple blocks of integrated IP rather than single blocks and doing the integration yourself, which has played out well for companies like Virage Logic, Synopsys and Mentor Graphics.

Despite analyst predictions that independent IP vendors would disaggregate the market, the trend has gone the other way. It’s not that small IP development teams don’t produce great IP. It’s that the integration of that IP with other IP blocks and manufacturing processes is a lot more difficult than creating a single IP block.

From a business standpoint, this is a reflection of a new direction of consolidation. As markets shrink, consolidation occurs. But what has changed, rather suddenly and somewhat subtly, is the reason for this consolidation. It’s not based upon lack of business. It’s based upon complexity and the interaction of many pieces from multiple vendors. Moreover, rather than being confined to the edge of Moore’s Law, the problems felt at the most advanced geometries are now pervasive.

This is an interesting shift, and it should produce some interesting solutions over the next few years—not to mention some business upsets in unexpected places.

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year.

GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and UMC to semiconductor companies like IBM, STMicroelectronics and Samsung to EDA providers like Synopsys and Cadence.

Virtually anyone can become a member of the GSA, and given the list of members it appears that a good portion of the industry has signed on. But you have to get elected to the board of directors, which basically puts you into the center of the customer and supplier ecosystem. The proof is in the attendance numbers. Average attendance at board meetings of non-profit organizations is roughly 50%. The GSA’s attendance is closer to 100%, according to GSA president Jodi Shelton.

For two board seats in two categories there are 13 different executives in the running from as many companies. One is for the broadly defined semiconductor board seat, where 10 different companies are competing. The second is a new category of value chain producers (VCPs), where eSilicon, Global Unichip, and Silicon 360 are each vying for the spot.

While most of this happens behind the scenes—the lobbying for votes with recorded messages and the campaigning to members—what’s interesting is the hidden message behind all of this. The GSA is representative of the industry, and increasingly no company can stand on its own. An SoC isn’t the work of a single company—even at big companies like Intel, IBM or Samsung—which means it’s now increasingly important to be at the center of the ecosystem to remain competitive.

That makes the stakes higher than ever before, and it means GSA elections should become even more hotly contested at every process node—most likely with new spinouts like the VCP definition. And like all complex designs these days, this should get very interesting.

–Ed Sperling

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their revenue going into the downturn.

There are five very good reasons for this:

1. The downturn has shown many companies they need to be hedged across multiple markets if they want to continue showing growth in future years. Because of the convoluted supply chain, which is spread across continents and across different design cycles, not all parts of the design chain feel the pinch at the same time. As a result, we’re seeing moves into a variety of areas such as Mentor pushing into Android devices and Synopsys moving into software prototyping.
2. Not all parts of the industry are poised for significant growth in the future. There will jam-up of competitors in some areas because there are far fewer design starts. While the design starts that do happen will be bigger and more complex, there will be fewer companies developing them because of the cost. In addition, there will be less creativity in other areas that were consistent revenue sources because rising complexity coupled with a lag in lithography technology is forcing more restrictive rules on designers. Just to get chips out the door at 32nm and beyond will require more regular shapes and layouts, which doesn’t bode well for a slew of players fighting for a shrinking place and route market.
3. The value has shifted from just hardware or software to hardware and software. Co-verification, software modeling and prototyping and even operating system and some application development is being done by chipmakers. Companies that can bridge these two worlds effectively will reap bigger rewards than those doing the same thing they were doing two years ago.
4. The pain points are getting more granular. While SoC design is moving to a higher level of abstraction, verification has more things to test. The models work great for blocks, but now those blocks have to be tested, as well. And they have to be integrated and share resources, particularly in multicore chips. Add in various power modes and power islands and complexity goes straight up and off the charts. That also has created new opportunities for startups to gain entry into the industry, and the big guys are struggling to either absorb them or compete against them.
5. There is growth in tangential markets, and far better security in reaching beyond the classic EDA world. Mentor’s push into DFM and test, mechanical analysis and wiring harnesses is a case in point. Synopsys’ push into IP and high-level synthesis are well beyond its normal flow. Even Magma has pushed into analog and mixed signal place and route.

As we emerge from this downturn—and we are still not fully emerged—these moves are likely to become even more pronounced. What is uncertain is just how the industry will look when these changes take root.

–Ed Sperling

The EDA world is either doing better than most segments of the economy or coming apart at the seams, depending upon your perspective and your definition of exactly what an EDA company is. But at least one trend seems clear: As we push into the world of system-level design from chip design and SoCs instead of ASICs, the high-level trend is broader companies with more complete integrated packages rather than lots of little pieces.

While this may cause all sorts of gyrations and lots of discomfort in the interim, the industry around system-level design tools ultimately will emerge significantly stronger if not overtly different. It has no choice. Either it begins eliminating pain for engineers developing incredibly complex chips or they’ll lose market share to companies like IBM and Toshiba, which already have their own proprietary tools, and the foundries, which easily could cobble together a suite of tools on their own.

To no small extent, Mentor Graphics and Synopsys are well along the path of creating much more integrated flows that reach well beyond the bounds of where they used to be. Cadence clearly sees the need to change, as well, which accounts for the board’s recent actions to boot all upper management—including longtime CTO Ted Vucurevich this week. He mysteriously has disappeared from the management roster, even though the company never announced his departure.

Cadence’s new CEO, Lip-Bu Tan, has more experience on the finance side than anyone since former CEO Ray Bingham, but he also has one other benefit. According to company insiders, he has very strong ties inside China, which Cadence’s board clearly sees as a growth opportunity.

Magma, meanwhile, has gone under a cloak of secrecy in recent months to develop its new strategy. Sources say the company is working on automating parts of the analog flow, but exactly what and how successful Magma will be in that space remains to be seen.

What happens to a number of startups along the way is another question. Our guess is that consolidation will begin in earnest when the economy hits bottom and begins climbing back from the depths of despair. The bigger question is where do the next startups get going. Silicon Valley will still be strong, but not all the VC money will end up there.

What do you think will happen next?

“Just because it’s difficult to do doesn’t mean it’s a differentiator.”

That succinct and rather meaty statement belongs to Aart de Geus at Synopsys, but most executives in the chip world have been spouting these kinds of revelations for months. There’s a fundamental shift underway, which is evolving from focusing on a single chip to seeing that chip as part of a system. The final product has become so complex that no single engineer can understand every facet of the development process with the same level of detail as in the past.

To many engineers, this is a career-changing concept. Understanding the underpinnings of chip design and development was considered invaluable, and the biggest rewards went to those who understood it best. That was then. This is now. Getting the job done quickly, with fewer people and fewer re-spins is paramount.

In many respects, tools like TLM 2.0 and IP-XACT work like a black box.  You don’t need to know all the details to make it work, which means an engineer with less training actually can do as much or more than someone mired in the old way of doing things. And clunky internally developed tools often are more of a hindrance than a help, even though the thinking among many managers is that they’ve already paid to develop the tools and therefore they’re free. They’re not. Inefficiency costs time and money.

And if this sounds like a huge change in the digital world, wait until it starts hitting the analog world. The economics of one-off designs, not to mention the time it takes to create them, are putting pressure on chip developers to adopt more standardized approaches. Digital was first, and even that hasn’t been an easy transition. Pushing from digital chips to complete systems, including application software, is still a huge challenge.

In the analog world, the whole design process has been stuck in the same place it’s been for the past several decades. The rule of thumb is that it takes 10 years to create a good analog engineer and it takes years to create a good analog design. As analog and digital find their way into the same system-level design process, no one can wait that long anymore. They have to work at the same process node—something most analog engineers will cringe at—and they have to be developed concurrently.

Automating development could shorten that time dramatically, but it will require wholesale changes in the ranks of established companies that have built a reputation on developing processes that age far more slowly than in the digital world. In the end, defining what is the best way of doing things is a business decision, not a scientific one—as painful as that realization may be.