At the distant forefront of research there is very little marketing. After all, what’s the point? Until recently, much of this stuff was theoretical physics, and products weren’t even a consideration.

It wasn’t until the past decade when we could actually see atoms. We had to theorize them. And it wasn’t until the past few years when we actually began taking stacked die seriously. But there are some new terms beginning to emerge on the distant horizon, and they indicate not only the marketing opportunities that ultimately may follow but the engineering challenges, as well.

One of the new terms to emerge is “tunnel FETs,” or TFETs. This fits right in with nanowires as a possible technology that will need to be considered for the most advanced digital processes when we begin approaching the next couple nodes following 14nm.

A tunnel FET, according to an Imec research paper, will include multiple horizontal gates, which will be critical for the ultra-low power and ultra-low voltage operation. It also has begun showing up in future projections at TSMC.

Carbon nanowires have been talked about for some time. Research is now beginning to ramp up on this technology. These are extremely thin wires—some even thinner than 1nm—that will be essential when process geometries shrink down to the sub-10nm range. This will create all sorts of interesting effects of course, many of which we haven’t even considered.

While this stuff may seem academic at this point, consider that the major foundries are working on 20nm, with lots of advanced designs in the pipeline at 28nm. Memory is expected to be below 20nm by next year, and work has already begun on 14nm—which for many applications may be the next node after 28nm.

This is the new wrinkle in design. Node skipping has become rampant because of the long tail of derivative designs required by a massive design investment. That economic shift will make these terms more relevant much more quickly, which means what was one distant theoretical research will now become required reading and research for companies looking to stay at the forefront of Moore’s Law. And it will even be relevant for companies working on stacked die that build on these advanced digital platforms.

Research has never had such immediate consequences. The only question now is what those consequences will be.

–Ed Sperling

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year.

GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and UMC to semiconductor companies like IBM, STMicroelectronics and Samsung to EDA providers like Synopsys and Cadence.

Virtually anyone can become a member of the GSA, and given the list of members it appears that a good portion of the industry has signed on. But you have to get elected to the board of directors, which basically puts you into the center of the customer and supplier ecosystem. The proof is in the attendance numbers. Average attendance at board meetings of non-profit organizations is roughly 50%. The GSA’s attendance is closer to 100%, according to GSA president Jodi Shelton.

For two board seats in two categories there are 13 different executives in the running from as many companies. One is for the broadly defined semiconductor board seat, where 10 different companies are competing. The second is a new category of value chain producers (VCPs), where eSilicon, Global Unichip, and Silicon 360 are each vying for the spot.

While most of this happens behind the scenes—the lobbying for votes with recorded messages and the campaigning to members—what’s interesting is the hidden message behind all of this. The GSA is representative of the industry, and increasingly no company can stand on its own. An SoC isn’t the work of a single company—even at big companies like Intel, IBM or Samsung—which means it’s now increasingly important to be at the center of the ecosystem to remain competitive.

That makes the stakes higher than ever before, and it means GSA elections should become even more hotly contested at every process node—most likely with new spinouts like the VCP definition. And like all complex designs these days, this should get very interesting.

–Ed Sperling

We’ll probably never know the full extent of the story, but it appears the board of directors at TSMC didn’t just rubber stamp Morris Chang’s title when it named him chairman and CEO last month.

Chang was always chairman, but he wasn’t CEO. He had bestowed that title on Rick Tsai several years ago, who was Chang’s heir apparent. Tsai was named president of the new business development organization last month, reporting to Chang.

While Chang is almost synonymous with the creation of the foundry business, market founders don’t always end up as the long-term leaders. Steve Jobs at Apple is a rarity, and even he got pushed out of the company once. Most of the other companies that created a new business sector didn’t finish first, and most of the other leaders who started companies in the tech business—at least in the last several decades—didn’t survive.

The foundry business is a particularly tough one. Foundries talk about service, depth of offerings, established processes at advanced nodes and half-node jumps. But the bottom line is it’s still differentiated on price, which is measured in cost per chip, yield (a measure of the stability of processes), time to market for top customers and the ability to avoid respins. And for the most part, that business takes place at older process nodes where the factors are the only differentiators.

That’s at least part of what’s driving the restrictive design rules at the front end of Moore’s Law. Getting chips out the door, on time and in decent enough yields, is a marketing tool, if nothing else, and if restrictive design rules are necessary to accomplish that then foundries will insist on them. The other driver is lithography, which makes designs even harder to tape out successfully because the laser beams used to etch the silicon right now are much wider than the line widths between the wires.

So what really happened at TSMC? Consider the following series of events. First of all, TSMC is having yield problems at 40nm while its competitors are churning out chips at 45nm. Second, the Common Platform folks have 40nm technology ready and waiting when it becomes competitively necessary to offer it—namely when TSMC begins offering it. And third, TSMC is now feeling the pinch of the Common Platform’s growing ecosystem and SMIC’s rollout of 45nm process technology.

Add those three factors up and it’s no wonder that TSMC is changing its top management. The return of Morris Chang to CEO apparently wasn’t just an honorary title. It was a necessary change.

–Ed Sperling