As the accelerating market of SoCs inevitably means a faster rate of adoption, system level designers are also faced with fragmenting markets, with new standards adopted and with multiple types of complex requirements in a system. The integration of IP (Intellectual Property) can be a boon, but there are caveats, as Caroline Hayes, Senior Editor reports.
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The quadrupling of resolution in 4k video opens up broadcast, gaming and other sectors to a world of mobility via the ubiquitous smartphone. By Caroline Hayes, Senior Editor.
Graphics processing is no longer a case of monochrome or color, but shading to add depth in computer games, digital signage or medical equipment.
Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 3 of 3 “Futures”, the guys discuss: adding IoT “intelligence at the node”; the Sensinode acquisition for intelligent protocols; wearables, MEMs and mixed signal RF sensors; and the Thrust of sensor-to-server.
A significant amount of innovation comes from smaller companies focused on one or just a few sectors of the market. A number of them, plus Synopsys, contributed to this forecast.
EDA grows by solving new problems as discontinuities occur and design cannot proceed as usual. Occasionally discontinuities create new markets for the industry.
Experts from ARM, Mathworks, Cadence, Synopsys, Analog Devices, Atrenta, Hillcrest Labs and STMicroelectronics cook-up ways to integrate analog with IoT buses.
When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts from ARM, Jama Software and Imec propose the answers.
System Companies are changes in development methods will be more obvious in 2015 together with higher percentages of mixed/signals designs.
Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 2, the guys discuss: ARM’s mbed/mbed OS and Cortex-M7; the easy path to the IoT is made easy by ARM’s new mbed environment. As well, Ian talks about heterogeneous cores and securing the IoT.
Videos/PodcastsWhy IP Providers Need the New 1149.1/JTAG
Imec’s mm Wave Motion Sensing Technology
Low Power Engineering
Is Hardware Really That Much Different From Software When is hardware really software? Are software flows less complex? Are hardware tools less...
Citizen Science and The Search for Sputnik IV: Part 1 The holiday season is once again upon us, and, as usual this time of year, my thoughts are...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.