Graphics processing is no longer a case of monochrome or color, but shading to add depth in computer games, digital signage or medical equipment.
Technology Features Archive
The challenge is to find ways to abstract with reasonable accuracy for different types of IP and different loads. Reasonable methods to parameterize power have been found for single and multiple processor systems, but not for more general heterogeneous systems.
I learned many things at Embedded World 2014, among which was the fact that the German word for safety and the word for security are the same (sicherheit). Only the context of the conversation will reveal which is being discussed.
The high tech experience is no longer limited to one device type as capital and complexity barrier breeches allow innovation in new markets.
A panel of experts from Cadence, Mentor, NXP, Synopsys and Xilinx debate the reality and causes of the apparently widening verification gap in chip design.
Shannon covers the last news in the semiconductor systems engineering industry and research developments for February 2014. This month’s highlights include the paper brain, MEMS and IEEE on Internet-of-Things (IoT) standards, Da Vinci themed design competition, and IoT at Embedded World.
In Part II of this series, semiconductor electronic leaders discuss how data-related IoT issues might disrupt organizational structures and supply chain relationships.
Console platforms move to profitability with services as mobile gaming faces challenges, while hardware technology affects software sales.
In response to security vulnerabilities, system level designers have made the security of data and content a prime objective in our connected lives
One of the joys of today’s electronics devices is that they are connected. However connectivity and sharing files can make a system vulnerable.
Low Power Engineering
vManager Reborn Metric driven design verification has finally come into its own. As I reported last year at...
Verification Gap or System-Level Issue? One of the panel discussions at the upcoming DVCon event deals with the alleged verification...
Videos/PodcastsIn Focus – System News for Feb. 2014
Nanotechnology Transforming Material Civilization
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
- Edward Thornton: Could you identify the author? It’s tough to understand if a Chip Design writer wrote this or...
- Drew Wingard: Wow! I wish that Sonics had been a big enough company to drive an IP standards organization that signed...
The Babylonian system au contraire, The xCORE XS1-L4-64 integrates four 32bit processor cores at a price under $3 that is comparable...
The Babylonian system that's because and thanks to The Babylonian system of mathematics ,the sexagesimal (base 60) numeral system. "From...
R Frank John, In Ireland the Croissants are terrible but the Guinness is really good. Your short piece energized me to...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.