As the accelerating market of SoCs inevitably means a faster rate of adoption, system level designers are also faced with fragmenting markets, with new standards adopted and with multiple types of complex requirements in a system. The integration of IP (Intellectual Property) can be a boon, but there are caveats, as Caroline Hayes, Senior Editor reports.
Technology Features Archive
The quadrupling of resolution in 4k video opens up broadcast, gaming and other sectors to a world of mobility via the ubiquitous smartphone. By Caroline Hayes, Senior Editor.
Graphics processing is no longer a case of monochrome or color, but shading to add depth in computer games, digital signage or medical equipment.
A discussion about IoT definition, need for standards, and security.
Tensilica Fusion DSP fits directly in IoT products
Physically aware synthesis techniques that can help accelerate the physical design closure process for high-performance, power-sensitive SoCs at 28nm and below.
Cadence has introduced its Innovus Implementation System, a physical implementation solution that aims to enable system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market.
In general, the industry is experiencing the need for what now has been started being called the “shift left” in the design flow. From a chip perspective, about 60% into a project three main issues have to be resolved.
The demand for shorter bring-up schedules and more efficient work flows are driving innovations by commercial providers of FPGA-based prototyping tools.
Since the very early days of ASIC design engineers have prototyped the ASIC using FPGA devices in order to debug and verify the design. The advantage is that the Device Under Test (DUT) runs at speeds that are equal or nearly equal those of the actual device.
Videos/PodcastsWhy IP Providers Need the New 1149.1/JTAG
Imec’s mm Wave Motion Sensing Technology
Low Power Engineering
Part II: The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP Part II of our tour through UVM reusability through TLM ports and the factory in the AMIQ...
The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP: Part I An interesting thing happened on the way to arriving at a completed article about the AMIQ...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.