eSilicon STAR platform delivers enhanced user experience and new capabilities that leverage IC design virtualization technology
Internet of Things (IoT) devices ranged from Bluetooth gateways and smart sensors to intensive cloud-based data processors and hackathons – all powered by ARM.
Experts from ARM, Mathworks, Cadence, Synopsys, Analog Devices, Atrenta, Hillcrest Labs and STMicroelectronics cook-up ways to integrate analog with IoT buses.
When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts from ARM, Jama Software and Imec propose the answers.
Low Power Design is now the main stream in IC development. There is no more a separation between plugged-in circuits and battery powered devices.
By Caroline Hayes, Senior Editor The twists and turns of FinFET In an earlier Deeper Dive (Nov. 21) we looked at how TSMC’s 16nm FinFET reference design was encouraging harmony among teams, as they work together to verify designs and accommodate the three dimensional transistor structure. In this edition, members of the design community are [...]
Examples in hardware-entangled security and neuromorphic processing show how technology can be further optimized to solve specific system and application demands.
The Cortex-M7 is really an extension of the Cortex-M4… designed for endpoints in automotive, Internet of Things and portable medical applications that will be expected to deliver 30 years’ of operation.
The wheels of industry roll on. Themes at Embedded World in Nuremberg were predictable, with automotive, industrial automation and IoT but there were some twists and revelations too.
In response to security vulnerabilities, system level designers have made the security of data and content a prime objective in our connected lives
Videos/PodcastsLegacy vs New IP – Trends in IOT JPG and Drone Applications
Engineering vs. Science in Public Policy
Low Power Engineering
Beginning the Discussion on the Internet-of-Space A panel of experts from academia and industry assembled at the recent IEEE IMS event to answer...
Cybernetic Human Via Wearable IOT UC Berkeley's Dr. Rabaey sees humans becoming an extension of the wearable IoT via neuron...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.