The December 2016 monthly tech travelogue visits the Internet of Space technologies and business viability.
Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook.
ASIC prototyping with FPGAs faces global development challenges in the hardware-software IoT and automotive markets.
IOT Devcon interview with Vivek Mohan at Silicon Labs examines standards vs. proprietary IOT connectivity.
Highlights include Si-based molecular scanners; cyber-security; automotive standard ISO 26262; SPIE Photonics; DVCon
John/Sean Travelogue for March 2016 – Highlights include Si-based molecular scanners; cyber-security; automotive standard ISO 26262; SPIE Photonics; DVCon.
CAST’s CEO Explains the Business vs. Technical Side of Semiconductor intellectual property (IP), especially as verification becomes a critical part of the entire IP package.
Intellitech’s CEO CJ Clark explains why the latest JTAG update brings much needed capabilities to IP providers and IC developers alike.
Motion sensing applications with mm wave technology at Imec is the topic of this interview between Liesbet Van der Perre, Imec Program Director of Wireless Communication, and John Blyler, VP and CCO at Extension Media.
Drawing on the lives of five renowned scientists, Mario Livio shows how even these geniuses made major mistakes and how their errors were an essential part of the process of achieving scientific breakthroughs. Dr. Livio was interviewed by John Blyler, Chief Content Officer at Extension Media.
Shannon covers the last news in the semiconductor systems engineering industry and research developments for February 2014. This month’s highlights include the paper brain, MEMS and IEEE on Internet-of-Things (IoT) standards, Da Vinci themed design competition, and IoT at Embedded World.
Videos/PodcastsInternet of Spaces for the IOT
Has The Time Come for SOC Embedded FPGAs?
Low Power Engineering
Beginning the Discussion on the Internet-of-Space A panel of experts from academia and industry assembled at the recent IEEE IMS event to answer...
Cybernetic Human Via Wearable IOT UC Berkeley's Dr. Rabaey sees humans becoming an extension of the wearable IoT via neuron...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.