By Caroline Hayes, Senior Editor The twists and turns of FinFET In an earlier Deeper Dive (Nov. 21) we looked at how TSMC’s 16nm FinFET reference design was encouraging harmony among teams, as they work together to verify designs and accommodate the three dimensional transistor structure. In this edition, members of the design community are [...]
Round Tables Archive
What’s needed for 3D-ICs to flourish? asks Caroline Hayes, senior editor. Experts from Mentor Graphics, Altera and Synopsys have some ideas for future progress.
As the industry transitions from 2.5D to 3D-ICs, Caroline Hayes, senior editor, asked experts from Mentor Graphics, Altera and Synopsys for their view on what system designers need to consider in implementing 3D-ICs.
With new roles, IoT security will become even more important. Caroline Hayes, Senior Editor, asked Steve Kester, Shantnu Sharma (both AMD), Rich Rejmaniak (Mentor Graphics) and Rob Coombs (ARM) what is needed and how a secure IoT can be achieved.
Caroline Hayes, Senior Editor asked four industry experts, Carsten Elgert, Product Marketing Director, IPG (IP Group), Cadence, Tom Feist, Senior Marketing Director, Design Methodology (TF), Xilinx, Dave Tokic, Senior Director, Partner Ecosystems and Alliances, Xilinx, and Warren Savage, President and CEO, IPextreme (WS) about the pros and cons of IP reuse versus in-house IP.
David Shippy of Altera, Lawrence Loh from Jasper Design, Mentor’s Steve Bailey, and Drew Wingard from Sonics got together to discuss the issues inherent in connecting IP blocks whether in a SoC or on stack die architecture.
System-Engineered Design discusses the evolution and future of design for test (DFT) with Synopsys, OptimalTest, Mentor Graphics and Cadence Design Systems.
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
The military’s infatuation with SWaP-C begins to drive non-defense suppliers as myriad markets and applications need better-than-commercial.
The machine-to-machine (M2M) phenomenon is accelerating and is coming to just about any connected technology near you.
Videos/PodcastsWhy IP Providers Need the New 1149.1/JTAG
Imec’s mm Wave Motion Sensing Technology
Low Power Engineering
EDA Tool Reduces Chip Test Time With Same Die Size Cadence combines physically-aware scan logic with elastic decompression in new test solution....
Managing Complex Hardware-Software Systems - Online Course Engineering differs from project management especially in the age of hardware-software systems....
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.