By Caroline Hayes, Senior Editor The twists and turns of FinFET In an earlier Deeper Dive (Nov. 21) we looked at how TSMC’s 16nm FinFET reference design was encouraging harmony among teams, as they work together to verify designs and accommodate the three dimensional transistor structure. In this edition, members of the design community are [...]
Round Tables Archive
David Shippy of Altera, Lawrence Loh from Jasper Design, Mentor’s Steve Bailey, and Drew Wingard from Sonics got together to discuss the issues inherent in connecting IP blocks whether in a SoC or on stack die architecture.
System-Engineered Design discusses the evolution and future of design for test (DFT) with Synopsys, OptimalTest, Mentor Graphics and Cadence Design Systems.
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
The military’s infatuation with SWaP-C begins to drive non-defense suppliers as myriad markets and applications need better-than-commercial.
The machine-to-machine (M2M) phenomenon is accelerating and is coming to just about any connected technology near you.
Requirements for portable, low-power consumer devices, as well as energy-efficient embedded systems, drive MCU development and offer options for embedded engineers.
Cheryl Coupé Fueled by new technologies, sensors have become ubiquitous, providing better user interface experiences and more natural interaction with devices. Rapid advances in MEMS and related technologies are enabling some of the most fascinating, innovative product developments since the PC. But the pace of innovation drives challenges as well. Those range from sensor fusion [...]
Cheryl Coupé, Editor Machine-to-machine (M2M) capabilities—and challenges—are proliferating in transportation applications such as intelligent highway, railway control and fleet management systems. The days of isolated embedded transportation computers are long gone. These days, machine-to-machine (M2M) is on the move, and could be defined as anything from vehicle-to-vehicle, vehicle-to-road, vehicle-to-dispatch or even vehicle-to-passenger-device. Standards—in connectivity, board [...]
Cheryl Coupe, Managing Editor Experts discuss Intel challengers in high-performance, server-class processors, the move to 100G Ethernet and impact of new standards on ATCA-related markets. It’s clear that 40G ATCA products are hitting the mainstream, especially in mobile infrastructure (especially LTE/4G) and data center applications (cloud, anyone?). And while ARM and AMD are making strong [...]
Videos/PodcastsIn Focus – System News for Feb. 2014
Nanotechnology Transforming Material Civilization
Low Power Engineering
Unexplained Absence: An Engineer's Cautionary Tale You may have noticed, (I hope at least), that I havent written here in a while. Heres why....
Jasper on Verification Gap s there a verification gap? Or is it that too much time is being spent inefficiently on verification?...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
- Edward Thornton: Could you identify the author? It’s tough to understand if a Chip Design writer wrote this or...
- Drew Wingard: Wow! I wish that Sonics had been a big enough company to drive an IP standards organization that signed...
The Babylonian system au contraire, The xCORE XS1-L4-64 integrates four 32bit processor cores at a price under $3 that is comparable...
The Babylonian system that's because and thanks to The Babylonian system of mathematics ,the sexagesimal (base 60) numeral system. "From...
R Frank John, In Ireland the Croissants are terrible but the Guinness is really good. Your short piece energized me to...
Earle Rock on! All together or nothing , step up as one! Earle.
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.