First of three parts: What it is; what’s needed to make it work; why Moore’s Law doesn’t always apply; how it will be built; when it will ramp up; and who’s going to benefit and reap the profits.

Second of three parts: How chipmakers will differentiate; time-to-market issues; changes to the ecosystem; consumer concerns; standards; security.

Last of three parts: Who’s responsible when something goes wrong; security issues; local vs. cloud; re-usability of IP; what will speed up or slow down adoption.

First of three parts: What’s changed; the pros and cons of UVM; the evolving nature of complexity; three paths for verification; partitioning the verification; limits of formal, FPGA prototyping; relatively vs. absolutely correct.

Second of three parts: Different applications for tools; who’s doing the verification; automated assertions; the role of UVM; EDA opportunities and challenges; how things are really done.

Last of three parts: Verifying IP and software; using margin as a buffer; ‘happy gates’; deadly bugs; too many models; improving verification through better design.

First of three parts: IP qualification and verification; hierarchy of verification tasks; application-specific verification; re-using testbenches; knowledge transfer across the design flow; improving communication between hardware and software teams.

Second of three parts: Trust IP, but still verify it; what can go wrong; the danger of bugs in even non-critical IP; abstractions and use cases.

Last of three parts: Design variables for different markets; what’s good enough; uncertainty vs. innovation; big vs. small IP suppliers; future challenges with stacked die.

First of three parts: The need for speed and more complete tools; free tools vs. ASIC-level capabilities; timing closure problems; ASIC prototype vs. FPGA as the final product.