Graphene puts quantum computing in a spin; International super-superconductivity; Graphene structure research; China telematics changes course
Trends Research Archive
A summary of the results of a survey for developers of products in RF and analog/mixed-signal (AMS) ICs.
There is a shift occurring in the semiconductor market, driven by the consumer space, believes Warren Savage, president and CEO, IPextreme.
The bad new is that the electronic system level (ESL) segment of the EDA market still needs more robust standards. What’s the good news?
Electronic System-Level (ESL) design is a dynamic process but will it adapt to the changing requirements of complex IC and higher systems?
In wireless, wireline and financial big-data applications, moving all those packets needs prodigious FPGA resources, not all of which Altera had before its recent series of acquisitions, partnerships and otherwise wheeling-and-dealing.
Chris A. Ciufo, Editor-in-Chief Of five significant PCI Express announcements made at this week’s PCI-SIG Developers Conference, two are aimed at mobile embedded. It’s about time. The big news from the PCI-SIG is speed. From PCI to PCI Express to Gen3 speeds, the PCI-SIG is an industry consortium that lets no grass grow for long. [...]
Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it.
Chris A. Ciufo, Senior Editor Figure 1: Intel and the Linux Foundation collaborated on Tizen, an open source HTML5-based platform for smartphones, IVI, and other embedded devices. Samsung hedges Apple, Google bets with Intel’s HTML5-based Tizen Just when you thought the smartphone OS market was down to a choice between iOS and Android, Intel-backed Tizen [...]
Panelists from industry, national laboratories, and the Portland State System Engineering graduate program recently gathered for an open forum on model-driven engineering.
Videos/PodcastsLegacy vs New IP – Trends in IOT JPG and Drone Applications
Engineering vs. Science in Public Policy
Low Power Engineering
SEMI Pacific NW Breakfast Forum: The Future of Communication Attention â Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another...
How can the Chip Community Improve the Industry for IOT Designers? Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.