By Vipin Tiwari

Many chip designers are exploring adaptive voltage scaling (AVS) techniques, in which they tradeoff the excess performance from “fast” wafer lots with lower dynamic power by using lower voltage operation. This technique reduces overall chip power consumption while meeting the “typical” performance targets.

But the tradeoffs aren’t quite as clean as they look from 60,000 feet. With AVS, every chip has to undergo a voltage sweep test to find the minimum voltage level at which the “typical” performance target can still be met. On top of that, the board designers need to have a variable power supply.

Put it all together and the real cost of using AVS at the design/development, package, board and silicon test levels are far less clear. What’s your experience? We want to hear from you.

Vipin Tiwari is senior manager of strategic product planning at Virage Logic