Issues In SoC Methodology
Large variations in device characteristics pose a significant design challenge as CMOS technology scales down to 32nm and beyond. Traditional methods of worst-case scenario analysis will not give you a reasonable parametric yield, so designers are quickly moving toward statistical design methodology and statistical modeling to account for large random variations.
Although statistical design methodology and modeling offers enormous potential, designers may not be ready to fully deploy this methodology at the SoC level. We don’t even know all the possible pitfalls yet, but here is a list of some important questions to consider:
• Will productivity take a hit because EDA tools aren’t ready for this shift?
• How accurate are the statistical design models provided by foundries?
• What are the tradeoffs between parametric yield and performance?
As with all new approaches, there are more questions than there are answers. The problem this time is that none of answers is simple or definitive.
What’s your experience with this approach?
–Vipin Tiwari
Tags: Virage Logic