http://chipdesignmag.com/sld/tiwari Deep Insights for Chip Architects and Engineers Fri, 30 Apr 2010 02:57:12 +0000 hourly 1 http://wordpress.org/?v=3.0.4 http://chipdesignmag.com/sld/tiwari/2010/04/22/who-does-what/comment-page-1/#comment-19 Tom Hackett Fri, 30 Apr 2010 02:57:12 +0000 http://chipdesignmag.com/sld/tiwari/?p=69#comment-19 If pre-verified IP is a requirement, then it must be asked “Pre-verified to do what?” Complex interfaces like PCIe Gen3 have multiple possible implementations. Even old dogs like Ethernet have many new features and interface possibilities. Rarely if ever will any IP cover all possible variations. Just as speed, power, and area “metadata” figures have become searchable IP selection criteria on ChipEstimate.com, new criteria describing verified functionality also need to be established to assist the SoC integrator in selecting the right IP for the target application. If pre-verified IP is a requirement, then it must be asked “Pre-verified to do what?” Complex interfaces like PCIe Gen3 have multiple possible implementations. Even old dogs like Ethernet have many new features and interface possibilities. Rarely if ever will any IP cover all possible variations. Just as speed, power, and area “metadata” figures have become searchable IP selection criteria on ChipEstimate.com, new criteria describing verified functionality also need to be established to assist the SoC integrator in selecting the right IP for the target application.

]]> http://chipdesignmag.com/sld/tiwari/2010/03/25/the-rising-risk-of-failure/comment-page-1/#comment-15 System-Level Design » Blog Archive » Blog Review: March 31 Wed, 31 Mar 2010 14:13:03 +0000 http://chipdesignmag.com/sld/tiwari/?p=62#comment-15 [...] Logic’s Hezi Saar examines the rising risk of failure in the communications market, which is where the majority of [...] [...] Logic’s Hezi Saar examines the rising risk of failure in the communications market, which is where the majority of [...]

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