What’s The Rush?

June 24th, 2009

By Vipin Tiwari

Most of the device manufacturers are moving to high k/metal gate for the 32nm and 28nm process nodes.

On paper, this seems like a clear-cut decision. The technology reduces static leakage or boosts performance. In some cases, it can accomplish both. In others, it can provide significant gains in one or the other. It’s an extra knob to adjust for chipmakers, depending upon what they’re making and which market they’re making it for.

But from the manufacturing side, it’s going to be a race against time to be ready with process qualifications for next-gen products using high k/metal gate technology. And if all the pieces aren’t in place, that could cause needless delays.

It’s clear that the current Poly-SiON technology with strained silicon doesn’t make sense for 22nm. At that process node, device manufacturers will have no choice but to move to high k/metal gate or some other combination of technology that could even include 3D structures such as finFETS.

But what do companies do at 32nm and 28nm? Is the extra cost of high k/metal gate really warranted and necessary? And what won’t be ready in time?

These are important questions, and so far there aren’t many answers.

–Vipin Tiwari is senior manager of strategic product planning at Virage Logic

This Stuff Is Tougher Than It Looks

May 27th, 2009

By Vipin Tiwari

Vipin TiwariMany chip designers are exploring adaptive voltage scaling (AVS) techniques, in which they tradeoff the excess performance from “fast” wafer lots with lower dynamic power by using lower voltage operation. This technique reduces overall chip power consumption while meeting the “typical” performance targets.

But the tradeoffs aren’t quite as clean as they look from 60,000 feet. With AVS, every chip has to undergo a voltage sweep test to find the minimum voltage level at which the “typical” performance target can still be met. On top of that, the board designers need to have a variable power supply.

Put it all together and the real cost of using AVS at the design/development, package, board and silicon test levels are far less clear. What’s your experience? We want to hear from you.

Vipin Tiwari is senior manager of strategic product planning at Virage Logic