By Hezi Saar
The abundance of battery-operated mobile electronics is driving the need for reducing power consumption in electronics and ICs and has been the design focus in recent years. The need was not only fabricating ICs in a low-power process that operates at lower supply voltages and reduces leakage, but employing special techniques to reduce overall system power. These techniques include utilizing low-power modes, voltage and frequency scaling, architecting the system in power islands, clock gating, using multiple voltage thresholds, and power-trimming options.

Social networking has enabled new ways of sharing content. Specifically, generating high-quality videos is made possible with affordable gadgets that make it easy to upload to the network. The next big wave in mobile electronics is delivering high-bandwidth content from a variety of sources such as the Internet, a camera, and storage to the display or a removable card. Also, the ability to transmit content wirelessly or via cable to destinations such as the Web, TV and computers is required so content can be consumed anywhere.

The problem is the amount of time it takes to transmit this high-bandwidth content. High-bandwidth content needs to be streamed from end to end, but there can be multiple bottlenecks. If we look at one instance of content flowing from PC via a USB cable to a storage device, the limiting factors in the mobile device are the interfaces: SATA, USB and SD. If we look at a camera or wireless network streaming data to the mobile device, it is using slow interfaces.

The bottom line is that it takes minutes to download a standard HD movie from device to device, and similarly to transmit over the wireless networks, while user the experience demands content delivery to be downloaded in seconds. This need for speed (or should we call it throughput?) is only possible with the deployment of high-speed interfaces.

The deployment of high-speed SerDes standards will allow increased capacity of the entire chain serving the mobile-device consumer from end to end. MIPI specifications such as Camera Serial Interface (CSI), Device Serial Interface (DSI), Universal Flash Storage (UFS), or DigRF, will drive increased bandwidth in the mobile device in the near future and will solve the bottleneck between baseband, application processor, camera, display and storage. MIPI specifications coupled with bandwidth increases in high-speed interfaces such as USB and HDMI will enable sharing streaming videos quickly and easily to enhance the user experience and adapt it to today’s tastes.

–Hezi Saar is senior product marketing manager for Virage Logic’s SiPro Advanced Interface IP Product Line.

By Henk Hamoen
Complex multimedia ICs these days need to be able to support up to hundreds of combinations of use-cases. Each use-case has its unique set of combinations of data-streams to and from IPs and subsystems and off-chip DDR. Each IP has its typical requirements as well: CPUs require low-latency access, while for audio and video streaming needs to be efficient and need a guaranteed (high) throughput.

For system architects these are items of real concern. Will all the use-cases fit in the proposed SoC architecture? How will CPU requirements be served? What are the bandwidth guarantees for low-latency traffic? Can the system at the same time serve high-bandwidth audio and video traffic towards DDR memory? How much buffering and spare DRAM capacity will be reserved (over-design to prepare for the unknown)? In other words, how will the bandwidth requirements in various parts of the system still be guaranteed at the SoC level?

A smart arbiter that bridges on-chip interconnects and a DRAM controller is the solution. This enables architects to make conscious decisions regarding buffer-sizing and allocating DRAM capacity since the available bandwidth is now managed at the right level.

The benefits of the arbiter are clear:

Reduced system cost: The architect can make his design predictable, eliminating the need to over-design and reserve headroom. The system will work with less external DDR memory.

Improved product quality: A predictable behavior of real time functions in a system makes the system robust.

Speeded-up system integration: Programming the required bandwidth guarantees rather than tweaking priorities removes the need for trial and error exercises consuming expensive resources from the project.

Conclusion: With a smart arbiter that guarantees system performance, SoCs will become more robust and predictable while cost for external DDR can be reduced.

–Henk Hamoen is product marketing director at Virage Logic

By Mike Thompson
As companies increasingly rely on third-party IP providers, the challenge of integrating and verifying all the supplied IP from multiple suppliers is becoming much more important—and much more difficult.

What’s driving these changes are increasing complexity, limited budgets and the need to get to market more quickly—a triple play that becomes increasingly difficult at each new process node. And just to add to that challenge, device makers are now asking SoC developers to generate the silicon, the software that runs on it, and to make sure it’s all tested and that it’s reliable.

Just ensuring the IP is qualified for the same manufacturing process or voltage isn’t enough anymore. The software has to be integrated too—everything from efficient device drivers all the way up to complete software stacks. This can get particularly tricky when it comes to heterogeneous multicore implementations and platforms that run multiple operating systems.

Nevertheless, these platforms are becoming increasingly important as the conflicting requirements for increasing computing power and functionality on the one hand, and lower power on the other, lead to heterogeneous multicore solutions consisting of powerful general-purpose processors with specialized control or digital signal processors utilizing an optimal power-to-performance ratio.

These are difficult issues with very complicated technology, and they all have to work together seamlessly, be delivered on time, and on budget. The only way that can happen is with pre-integrated and pre-verified IP and a solid understanding of where to draw the line between what gets done in-house and what gets done on the outside—and by whom.

–Mike Thompson is director of product marketing at Virage Logic

By Karen Parnell

The trend toward everything-consumer means everything at the lowest possible price for the buyer and the highest volume for the seller. For audio that traditionally has dictated two different markets, one at the very high end and another at the mass-market price point.

That’s all changing. Sound no longer can be just “good enough.” It has to be all-encompassing, rich, deep and impactful in all cases, whether it’s for music, movies or gaming. As a result, designers now face the challenge of delivering great-sounding audio with no cost adders.

So how do you solve this dilemma? One answer is audio post-processing. While designers need the capability to enable existing audio transducers to sound exceptional, they also need to save on overall BOM costs. Allowing designers to select even lower-cost speakers and amplifiers – without compromising audio quality – is key, so finding the right “product mastering tools” to ensure the best possible sound from an existing set-up to optimize the audio quality are important.

–Karen Parnell is a product marketing director at Virage Logic

By Marco Jacobs

Codecs heavily compress real-world speech, audio, and video data. This compression greatly saves on transmission bandwidth and storage space. Without codecs, we’d only be able to receive a handful of channels on TV instead of the hundreds we’re used to now. We wouldn’t be able to make penny-a-minute global phone calls, and our DVDs would only store a few minutes of video instead of a whole movie.

By far the majority of codecs have been standardized. This ensures that data that has been captured on one device can be played back on another device, resulting in devices that are interoperable. The standardization effort involves many researchers working for several years, inventing clever compression algorithms to remove as much of the redundant and irrelevant information as possible. After years of discussion and evaluation of the best algorithms, the codec standard is frozen, gets published, and is ready for licensing to implementers.

It’s important to realize, however, that while a great deal of effort goes into this standardization process, not all codecs that implement a given standard are equivalent. Only the bitstream data—that information which the encoder and decoder exchange—is standardized, not the encoder or decoder itself. There’s actually a lot of freedom when implementing the codecs, and a lot of hard work and bright engineering ideas are required to develop a high-quality one. When licensing a codec, you would be wise to carefully evaluate the quality, performance and ease of use. Here are some things to consider:

Quality refers to both the audio or video quality of the compressed and consecutively decompressed data, as well as to the quality of the implementation. Is the codec robust to bit errors? Will it continue operating when it receives invalid data or data containing transmission errors, or will it hang? Will errors pop and crackle in the user’s ear, or will he hardly notice they’re there? Has the codec been certified? Does the codec work as advertised? Unfortunately, many codecs on the market are often incomplete or of low quality.

Performance can be measured using different metrics and under a wide variety of circumstances. What are the processor load, memory footprint and I/O requirements? What’s the performance in a real-world system where memory access latencies are often high, and bandwidth is constrained. Also, be aware of the bitstreams that were used to measure the above parameters. Were the streams carefully crafted to show good performance or are they real-world and difficult streams that really stress the system? A codec’s performance typically varies greatly based on the complexity of the bitstream.

Ease of use is the final important aspect. How easy will it be to integrate the code into your existing systems? How flexible and modular is the design? Will you have access to the source code, or is the codec provided as a binary only? Source code can be compiled for size or speed, and gives you the capability to extend and adapt the codec to meet specific (future) needs. Furthermore, looking through the source code is like opening the hood of a car. You can really get a good look at what’s inside. Also, if the codec isn’t working, is hardware or software to blame? You don’t want to get caught in a finger-pointing game between the codec vendor and the hardware vendor.

So when your next SOC needs to support a new coding standard, remember that not all codecs are created equal. Choose your codecs wisely, and make sure you learn everything you can about the supplier.

–Marco Jacobs is the product line manager for ARC processors at Virage Logic.

By Hezi Saar

The evolution of standards-based interfaces in mobile semiconductor markets and the maturity of the Mobile Industry Processor Interface (MIPI) standard is driving increased adoption rates for mobile applications. So why only now?

While the benefits of system-level standardization are evident, MIPI comprises a family of standards that have been developing over the past few years. It’s not just a single standard. It’s a collection of them, and included in those standards are display and camera interfaces.

To some extent, this is like the semiconductor industry keeping pace with the added functionality of mobile devices. While Moore’s Law has allowed additional functionality, the industry that benefited from that functionality has yet to embrace the standards that have followed. In addition, the MDDI standard was developed in parallel, and that could be perceived as a competing standard. These days, the path to MIPI adoption is clear at least on the mainstream needs that were developed in past years. MIPI has reached maturity level on the D-PHY specifications as well as Camera Serial Interface and Display Serial Interface controllers, as these are the most popular interfaces in mobile electronics and soon will be a “must have” standard for any mobile semiconductor device–especially on the camera and display interfaces.

The question is how a semiconductor device can quickly get these standards supported, especially when high-speed, low-power SerDes (such as D-PHY) is not their core competency. One thing that will help is proven IP that covers the MIPI D-PHY and controller camera and display standards on common processes.  This will allow easy, rapid, low-risk implementation that will enable semiconductor vendors to jump on the MIPI bandwagon and capture market share in this evolving market.

–Hezi Saar is the SiPro senior product marketing manager at Virage Logic.

Large variations in device characteristics pose a significant design challenge as CMOS technology scales down to 32nm and beyond. Traditional methods of worst-case scenario analysis will not give you a reasonable parametric yield, so designers are quickly moving toward statistical design methodology and statistical modeling to account for large random variations.

Although statistical design methodology and modeling offers enormous potential, designers may not be ready to fully deploy this methodology at the SoC level. We don’t even know all the possible pitfalls yet, but here is a list of some important questions to consider:

• Will productivity take a hit because EDA tools aren’t ready for this shift?
• How accurate are the statistical design models provided by foundries?
• What are the tradeoffs between parametric yield and performance?

As with all new approaches, there are more questions than there are answers. The problem this time is that none of answers is simple or definitive.

What’s your experience with this approach?

–Vipin Tiwari

By Vipin Tiwari

Many chip designers are exploring adaptive voltage scaling (AVS) techniques, in which they tradeoff the excess performance from “fast” wafer lots with lower dynamic power by using lower voltage operation. This technique reduces overall chip power consumption while meeting the “typical” performance targets.

But the tradeoffs aren’t quite as clean as they look from 60,000 feet. With AVS, every chip has to undergo a voltage sweep test to find the minimum voltage level at which the “typical” performance target can still be met. On top of that, the board designers need to have a variable power supply.

Put it all together and the real cost of using AVS at the design/development, package, board and silicon test levels are far less clear. What’s your experience? We want to hear from you.

Vipin Tiwari is senior manager of strategic product planning at Virage Logic