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Imec Reports Low-Power IP Blocks for 5G

Tech solutions for a smart world featured hardware and software innovations at the ITF Southwest Asian event.

Tech Travelogue June 2017 – Moore-Metcalf, IOT Chasm, Mechanical Design and 5G

Topics include the trends at DAC, Moore-Metcalf laws and the IOT Chasm, mechanical CAD in EDA and the continuing move toward systems.

Manufacturing Challenges 3D NAND Deployment

Jim Feldhan, president of Semico Research and veteran semiconductor analyst, shares his views on the challenges of moving from 2D planar to 3D NAND flash.

Silvaco - SOC Soln's Acquisition Reflect Systems Trend in IP

With completion of the Silvaco acquisition of SOC Solutions, Electronic System Design sat down with the principals from each company to talk about the future.

EDA in the Age of the System

Learn from other industries to gain a system's perspective was the reoccurring theme of Garysmith EDA analyst Laurie Balch’s pre-DAC address.

IOT Requires Shared Cloud and Embedded Connections

Mentor's Warren Kurisu explains how edge embedded and cloud connections (via Microsoft Azure) enables quick IOT development then demos a bio-metric game.

Hardware vs Software in IOT Security

Mike Mackey from CENTRI Technology, explains key IOT hardware-software security issues from TPM and PUFF to SSH and authentication. (IOT Devcon)

Gallium Nitride for Power Applications

X-FAB and Exagan fabricated GaN transistors on 200 mm silicon wafers

IP Fingerprinting Initiative from the ESD Alliance

ESD Alliance’s Fingerprinting Initiative increases legality of IP use.

Memory Subsystem Solutions Announced

Integrating a Network on Chip (NoC) with a memory controller provides increased system throughput.

Cadence Puts a Neural Network in a DSP

Cadence uses neural networks in a DSP for pattern recognition

Will Moore's and Metcalfe's Laws Cross the IOT Chasm?

The success of the IOT may depend more on a viable customer experience over the convergence of the semiconductor and communication worlds.

ESDA CEO Outlook Panel, not a Cause for Celebration

I found the 2017 EDSA CEO Panel Disappointing

SEMI Pacific NW Breakfast Forum: The Future of Communication

Attention – Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another half-day breakfast forum.

Cadence Builds a Winged Horse for Verification

Pegasus is a new massive parallel digital simulation engine from Cadence.

The Verification Times are Changing

A precursor of Portable Stimulus from Breker Verification Systems

Industrial IoT, a Silicon Valley Opportunity

The growth of industrial IoT presents opportunities in Silicon Valley

Chip and System Reliability Experts Assemble

The annual International Reliability Physics Symposium (IRPS) expands system reliability coverage to complement traditional microelectronics focus.

Portable Stimulus

Accellera is working on a method to make verification suites portable across verification tools.

How can the Chip Community Improve the Industry for IOT Designers?

Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry to streamline its processes for up and coming chip designers.

A Brief History of Verification

Design complexity has increased the cost of verification to the point that designers must now ask themselves how they can simplify the circuit.

Why is Chip Design for IOT so Hard?

Internet-of-Things (IOT) designers face a different set of challenges from their traditional ASIC and SOC brethren. Will the market be ready?

Legacy vs New IP - Trends in IOT JPG and Drone Applications

At REUSE, Meredith Lucky from CAST talked about the resurgence of legacy semi IP, parallelized JPG compressors for high def IOT and Drone system and more.

Optimizing Technology for IoT Systems – Adding Fingerprints and Brains

Examples in hardware-entangled security and neuromorphic processing show how technology can be further optimized to solve specific system and application demands.

Grant Pierce Named BoD Chair of the ESD Alliance

The Board of Directors of the ESD Alliance has named Grant Pierce CEO of Sonics as its Chair

DVCon Is a Must Attend Conference for Verification and Design Engineers

DVCon covers issues in verification and design in various application areas, from automotive to rf.

Apple vs Qualcomm. It Is More Than Money

EDA in the year 2017 – Part 2

Part 2 of the 2017 EDA predictions by leading exponents of the industry.

Engineering vs. Science in Public Policy

Senior policy advisor Dr. Guru Madhavan shares insights on the difference between engineering verses science and his path into the world of public policy.

Verification Joins the Adults’ Table

Verification is more than logic simulation

Beginning the Discussion on the Internet-of-Space

A panel of experts from academia and industry assembled at the recent IEEE IMS event to answer critical questions are the role and impact of RFIC technologies.

Cybernetic Human Via Wearable IOT

UC Berkeley's Dr. Rabaey sees humans becoming an extension of the wearable IoT via neuron connectivity at recent IEEE IMS event.

EDA in the year 2017 – Part 1

Part 1 of 2017 projections from EDA leaders

EDA has not been successful at keeping its leaders

The EDA industry must do a better job at keeping its best and brightest

A Holistic Approach to Automotive Memory Qualification

The Robustness Validation approach in design of automotive memory components addresses reliability and safety margins between design and actual application.

DVCon is a Worldwide Conference

The DVCon conference has now solid traditions not only in the USA but also in Europe, India, and next year will start flowering in China.

Specialists and Generalists Needed for Verification

Specialists and Generalists needed for design verification today but they may not be in the future.

Internet of Spaces for the IOT

The December 2016 monthly tech travelogue visits the Internet of Space technologies and business viability.

New Event Focuses on Semiconductor IP Reuse

Unique exhibition and trade show levels the playing field for customers and vendors as semiconductor intellectual property (IP) reuse grows beyond EDA tools.

Siemens Acquisition of Mentor Graphics is Good for EDA

Siemens acquisition will be good for Mentor Graphics and EDA

SoS Meets SoC as Siemens Buys Mentor Graphics

System-of-Systems (SoS) company Siemens significantly expands with acquisition of Mentor Graphics System-on-Chip (SoC), board-level and automotive technologies.

Innovations And Ideas From ARM TechCon 2016

This year’s event featured the new owner – Masayoshi Son, numerous security features, new IOT Cortex cores and updated third-party platforms.

ARM TechCon is the Model for Future Successful Conferences

ARM IP users find at ARM TechCon everything they need to successfully complete a design.

World of Sensors Highlights Pacific NW Semiconductor Industry

Line-up of semiconductor and embedded IOT experts to talk at SEMI Pacific NW "World of Sensors" event.

Has The Time Come for SOC Embedded FPGAs?

Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook.

Kilopass Unveiled Vertical Layered Thyristor (VLT) Technology for DRAMs

VLT Technology Eliminates Refresh Entirely While Delivering Lower Power, Cost and Manufacturing in Logic Compatible CMOS Processes.

Cadence Addresses Security in SoC

The core computation engines in secure SoCs need to consider not just the processor itself, but also how the interaction with other hardware features are implemented.

Interview with Pim Tuyls, President and CEO of Intrinsic-ID

Continuing the coverage on security here is the opinion from Intrinsic-ID

eSilicon Fully Automates Semiconductor IP Selection and Purchasing

eSilicon STAR Navigator includes automated, online quoting and purchasing capabilities for memory IP and I/O libraries.

IEEE Governance in Division

Will a proposed amendment modernize the governance of one of the oldest technical societies or transfer power to a small grouper of officials?

Mixed-Signal Platform Extends Charging

Mixed-signal platforms such as Silego's GreenPAK simplifies the design of an extended battery charger with minimal external components.

An interesting White Paper from S2C

S2C's white paper is of particular interest to designers that use FPGA based prototyping in their development of SoC designs.

ARC Processor summit in Santa Clara

Synopsys is holding its second ARC Processor summit on September 13 at the Santa Clara Marriott.

Has The Time Come for SOC Embedded FPGAs?

Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook.

Increasing Power Density of Electric Motors Challenges IGBT Makers

Mentor Graphics answers failure mode questions and simulation-testing for IGBT and MOSFET power electronics in electronic, hybrid-electronic vehicles (EV/HEV).

Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License

Accellera puts its SystemC material under Apache 2.0 license

Hardware Based Security

SRAM PUF from Intrinsic-ID provides a hardware based security solution.

Reverse Acquisition

SoftBank acquires its own master.

Verification Choices: Formal, Simulation, Emulation

In SoC verification Formal, Logic Simulation, and Emulation are not mutually exclusive, but must be made to coexist.

FPGAs for ASIC Prototyping Bridge Global Development

ASIC prototyping with FPGAs faces global development challenges in the hardware-software IoT and automotive markets.

The powertrain evolution rolls on as CPUs develop

Automotive design is changing, to meet environmental, performance and consumer demands. Richard York, Vice President of Embedded ARM, tells Caroline Hayes how the company is meeting the powertrain evolution and if electrification has a future.

Open Standards to Open up the IoT

As the IoT expands, the need to remotely manage devices on a variety of networks - to provide reliable smart homes, offices, smart metering and medical devices - requires a common ...

The ARM – Softbank Deal: Heart Before Mind

SoftBank offer to purchase ARM does not look financially savvy.

Bluetooth 5 extends the IoT but remains low power

The latest version of the Bluetooth standard, Bluetooth 5, is expected to be released late 2016 / early 2017. Its increased operating range will allow faster data transfer and updates beyond its present confines to extend the IoT into realms outside the home. By Caroline Hayes, Senior Editor.

Clarifing Embedded IOT Connectivity Confusion

IOT Devcon interview with Vivek Mohan at Silicon Labs examines standards vs. proprietary IOT connectivity.

DAC Official Results Are In

DAC results in Austin were good, but the press release did not emphasize the right numbers.

DAC: The Day After

One EDA Company Embraces IP in an Extreme Way

Silvaco’s acquisition of IPextreme points to the increasing importance of IP in EDA.

GarySmith EDA without Gary

The EDA industry must grow by addressing new markets.

Garage sale at UBM

A new world for old publications. UBM divests itself of well known titles.

Cadence's Allegro and Orcad Updates

Cadence updates PCB design tools while DAC continues to ignore this market

Collected Thoughts About DAC

Collected answers to questions I have heard over the years about DAC.

ESDA to Host System Scaling Forum

ESDA hosts a presentation by Herb Reiter on system scaling

Watching Processor IP Trends in the Smart Wearable Market

As shipments of wearable devices continue to rise, smartwatches have evolved to be one of the most popular devices in this sector. To make the most of a projected 42.8% compound annual growth rate (CAGR) developers are examining what qualities will be needed to drive adoption.

Newest Arduino Brings Wi-Fi and ARM to a Trim New Form Factor

Makers can choose from multiple development platforms for the Internet of Things (IoT), many of which feature processors based on ARM design cores. Mark Woods, ARMs Applications Architect and Maker, discusses how the average maker, regardless of whether theyve a degree in electrical engineering or not, can get started on a project.

Bluetooth Low Energy Extends the Reach of Wireless Microcontrollers in the IoT

The role of Bluetooth Low Energy in embedded microcontrollers is opening up design, applications and services to users in the home and industry. Caroline Hayes (CH) asks Paul Williamson (PW), General Manager, Wireless Business Unit at ARM how the technology is changing the IoT rulebook.

How to Jump Start Custom SoCs with ARMs DesignStart Portal

Custom System on Chip (SoC) devices are becoming a cost-effective alternative to the traditional discrete IC board designs. ARM provides the DesignStart portal on its website, offering free of charge access to semiconductor IP for the design of custom SoCs, with low-cost licensing for the commercialization phase. IP includes the ARM Cortex-M0 processor and ARM Artisan Physical IP solutions optimized for fabrication processes at leading silicon foundries.

Trends in Hyper-Spectral Imaging, Cyber-Security and Auto Safety

Highlights from SPIE Photonics, Accellera’s DVCon and Automotive panels focus on semiconductor's changing role in emerging markets.

Lucio Lanza Joins ESDA Board

Dr. Lucio Lanza brings expertise andvision to the ESDA Board.

Fit-for-Purpose Tools Needed for ISO 26262 Certification

Both the product development process and third-party tool “fit-for-purpose” certification are needed for Automotive ISO 26262.

Highlights include Si-based molecular scanners; cyber-security; automotive standard ISO 26262; SPIE Photonics; DVCon

John/Sean Travelogue for March 2016 - Highlights include Si-based molecular scanners; cyber-security; automotive standard ISO 26262; SPIE Photonics; DVCon.

Business vs. Tech Side of Semi IP

CAST's CEO Explains the Business vs. Technical Side of Semiconductor intellectual property (IP), especially as verification becomes a critical part of the entire IP package.

Cadence Releases Next-Generation Virtuoso Platform

Cadence has chosen to retain the user interface of the Virtuoso custom design product while adding enhancements that make it perform as a new product.

EDA Consortium Renamed Electronic System Design Alliance

EDAC changed its name to ESDA.

Custom Compiler Shortens Layout of FinFET Circuits

Custom Compiler allows visual layout of circuits containing FinFET structures.

Register Automation: A visit with Semifore

Semifore found a good corporate life developing and maintaining Register Automation tools.

Future Challenges in Design Verification and Creation

With the growing introduction of Internet of Things (IoT) devices and applications, the issues of security and safety are becoming requirements to be verified.

ONeSpin Solutions Introduced at DVCon

OneSpin Solutons launched

New Test Compression Technology Reduces Test Time

2D Elastic Compression enables test time to be reduced by up to 3X without any impact on compression wirelength or fault coverage.

General Chair Shares Insights on DVCon 2016

Chair Yatin Trivedi highlights the upcoming US chip design-verification show and differences with European and Asian DVCon events.

DVCon U.S. 2016 Is Around the Corner

DVCon U.S. addresses pressing subjects in design and verification methods.

The Search for the Executable Specification

A properly formed test suite is a way to apply Agile methods to hardware development.

EDA Tool Reduces Chip Test Time With Same Die Size

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean?

Technology Implications for 2016

More predictions for 2016 dealing with specific product segments.

Managing Complex Hardware-Software Systems - Online Course

Engineering differs from project management especially in the age of hardware-software systems. Learn how with plenty of examples in the online credited course.

The EDA Industry Macro Projections for 2016

Instability in oil prices, the Middle East wars and the unpredictability of the Chinese market will indirectly influence the EDA industry.

The Dangers of Code Cut-Paste Techniques

A common coding practice can lead to product efficiency but also software maintenance nightmares and technical debt.

Advanced-Node Designs in 2016 and Beyond

At advanced nodes, the main concerns are around higher speed and lower power, which FinFET 14nm and 16nm both provide.

EDA World Leadership

American companies have been the leaders of the EDA industry since its inception.

Imagination Talks about RFIC, IP, Embedded IoT and Fabric-based SoCs

Tony King-Smith of Imagination Technologies discusses the need for RF IC designers, IP platforms, IoT as the new embedded and fabric-based SoCs.

How to Drive a Successful IoT Application Design Project

Edge node devices in IoT are very complex systems that integrate analog and digital functions in silicon, package, and board and are controlled by software.

Autonomous Car Patches, SoC Rebirth, IP IoT Platforms and Systems Engineering

Highlights include autonomous car technology, patches, IoT Platforms, SoC hardware revitalization, IP trends and a new edition of a systems engineering classic.

Mentor Graphics Comments on Signal Integrity

Mentor Graphics answers questions on signal integrity analysis

The Year in Review: Thoughts on 2015

Marie Pistilli, Gary Smith, IoT: black and white 2015

Improving Emulation Throughput for Multi-Project SoC Designs

As design sizes grow, so, too, does the verification effort. Designers must boost the emulation throughput and design team productivity to manage on time delivery and achieve performance targets.

ARM TechCon, the Aftermath

ARM TechCon is where IoT becomes real, where you see MEMS on a mini PCB, where mixed signal designs are the norm.

Cadence Introduces Palladium Z1 Enterprise Emulation Platform

New Powerful Emulation Platform Introduced by Cadence

Arduino or Genuino from Intel

Intel partners with an Italian company to develop an educational tool.

The Race to 5nm

Cadence and imec work on 5 nm process node.

EDAC does Patents

An opportunity to learn about patents thanks to EDAC

Synopsys’ Relaunched ARC Is Not The Answer

The ARC world will remain small. Synopsys mark on the IoT will possibly be substantial but certainly not because of ARC.

Cadence Introduced Tensilica Vision P5 DSP

New Cadence Tensilica DSP offers higher computing speed with less power consumption, for mobile, drone, automotive, security, wearable, and IoT applications.

Coventor's MEMS+ 6.0 Enables MEMS/IoT Integration

Newest Version of MEMS Design Tool Accelerates Development of Customized, Highly Integrated Sensors for the Internet of Things.

Rapid Prototyping is an Enduring Methodology

Although one of the oldest methods used to verify designs, FPGA prototyping is still here today, and more and more it will continue to be used in the future.

CAST finds VIP in Egypt

CAST Inc. has joined forces with Boost Valley to develop and deliver IP verification solutions.

Horizontal and Vertical Flow Integration for Design and Verification

System design and verification are a critical component for making products successful in an always-on and always-connected world.

Design and Verification Need a Closer Relationship

Concurrent development and verification of designs is more efficient and increases corporate organizational strength.

UVM goes to the IEEE

The Accellera Ssytems Initiative has released its UVM 1.2 standard to the IEEE for official standardization as IEEE18700.2. The Universal Verification Methodology (UVM) is providing a common methodology for engineers using SystemVerilog for design verification.

A Point to Ponder from Gary Smith’s DAC Presentation

Different approaches to provide an integrated electro/mechanical development environment to increase EDA revenue.

System Design Enablement – Looking Beyond the Chip

System Design Enablement (SDE) will provide tools, design content, and services for the development of whole systems or end products.

Design Virtualization and Its Impact on SoC Design

At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC.

Veloce Power Application Enables Mentor/Ansys Collaboration

The Mentor/Ansys collaboration provides power analysis to emulation users.

Gary Smith’s DAC presentation: The Changing Landscape

Gary Smith’s DAC presentation engender debate

New ARM IP Tooling Suite Reduces Significantly SoC Integration Time

The new ARM suite addresses the most complex challenges associated with SoC configurability and assembly while reducing time to market.

Cadence Introduces Genus Synthesis Solution

Massively parallel architecture scales linearly beyond 10M instances while improving power, performance and area.

Immersive 3D Tech Highlights Display Show

Intel’s Curie hardware module and RealSense technologies were showcased by the company’s CEO Brian Krzanich at the Society for Information Display conference

"Safety Documentation Package" Boosts Updated Functional Safety in ARM Systems

The increased connectivity in cars, medical devices and industrial automation has led to a review of safety standards, which developers need to meet.

OneSpin Solutions Unveils 360LaunchPad a Unique, Third-Party Verification Solution

Advanced Formal Verification Technology Platform from OneSpin Used by Partner Companies in Range of New, Unique Verification Solutions.

Companies embrace mbed OS for IoT development

ARM's mbed OS has found support among several companies already, offering connectivity, security and a development path.

The Marketing Budget is an Investment, Not an Expense

Marketing is too often thought of as a sales support department instead of a critical tool to establish a corporate profile and a competitive product market position.

eSilicon Launches Integrated ASIC Design And Manufacturing Platform

eSilicon STAR platform delivers enhanced user experience and new capabilities that leverage IC design virtualization technology

Improved Power Management With Sonics' ICE-Grain

Hardware controlled power management is more efficient than CPU-based techniques.

Bob Smith Selected as EDAC Executive Director

EDAC is bound to grow under Bob Smith Leadership

HoT Love IP Event at DAC

Join the Love IP Party at DAC

CDC Verification: Using Both Static and Dynamic Checking is Key to Success

Clock domain crossing (CDC) verification has become a critical element for success in modern digital electronic designs. both Static and Dynamic Checking are needed to assure proper CDC verification.

The Car as an IoT Node: What are the Design Implications?

The intelligent car should be considered a node on the Internet of Things (IoT).

How Mesh Connectivity Will Make Buildings Brainier

Some of the “things” that make up the IoT are inside buildings, and making those things smarter has consequences for connected building automation. The concept of the smart hom...

New Innovative Chip Designs Mean Big Challenges for Chip Designers

Circuits are larger, margins are less at the atomic dimension and designers are looking for ways to squeeze performance and yield.

Cadence Introduces Indago Debug Platform

Cadence introduces Indago, a new debug platform and three related apps.

Cadence Introduced The New Tensilica Fusion DSP

Tensilica Fusion DSP fits directly in IoT products

Synopsys to Acquire Codenomicon

Synopsys is making another bold move with the announced acquisition of security software company Codenomicon based in Finland.

Intel Acquisition of Altera: the Worth of Rumors

Speculations on the reason Intel has to acquire Altera are off the mark.

Design Automation Is More Than EDA

Growth of the EDA industry means loosing the "E".

Yield Analysis: EDA Black Ops

Foundries rely on tools from PDF Solutions; designer should as well.

Using Physically Aware Synthesis Techniques to Speed Design Closure of Advanced-Node SoCs

Physically aware synthesis techniques that can help accelerate the physical design closure process for high-performance, power-sensitive SoCs at 28nm and below.

Cadence Introduces Innovus Implementation System

Cadence has introduced its Innovus Implementation System, a physical implementation solution that aims to enable system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market.

DVCon is the Primary Design and Verification Conference

DVCon has become the primary design and verification conference worldwide.

FPGA Prototyping Could Become Mainstream Again

FPGA prototyping is not just a thing of the past, before the introduction of emulators, it is a technique used today by many development teams. Given the imminent development and introduction o a large number of small systems in the IoT architecture, I expect that there will be even more use of FPGA prototyping.

The Various Faces of IP Modeling

Providing all the needed types of models to successfully integrate an IP component into an advanced SoC is more complex than one would think.

Saygus V2 Android Smartphone

Saygus V² (V Squared), winner of the CES 2015 Innovation Award, has 320 GB of storage, ARM-based Qualcomm Snapdragon 801, 21 MP camera, dual-boot capable, 2.5GHz quad-core processor, runs Android 4.4.4 KitKat....and more.

CES 2015: Expanding the Connected Experience

Power-efficient ARM technology is everywhere you are, expanding your connected life.

Interview with Pebble Watch founder

Getting the Pebble Watch to Market. A conversation with Eric Migicovsky, Pebble founder and CEO

You Ought To See This Webinar

The Webminar on IP Marketplace by eSilicon presents interesting material for chip designers and project managers.

Smart Bluetooth, Sensors and Hackers Showcased at CES 2015

Internet of Things (IoT) devices ranged from Bluetooth gateways and smart sensors to intensive cloud-based data processors and hackathons - all powered by ARM.

IP Components Are EDA Tools

Hardware IP component are used by engineers to design and develop hardware thus they are EDA tools.

ARM TechCon Videos: Interview with Ian Drew. Part 3: Futures.

Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 3 of 3 "Futures", the guys discuss: adding IoT "intelligence at the node"; the Sensinode acquisition for intelligent protocols; wearables, MEMs and mixed signal RF sensors; and the Thrust of sensor-to-server.

The eSilicon IP MarketPlace: Easy and Quick Integration of IP in Your Design

IP MarketPlace from eSilicon is an efficient way to choose memory IP adapt it to your design and produce all the fab information you need.

Next Year in EDA: What Will Shape 2015

A significant amount of innovation comes from smaller companies focused on one or just a few sectors of the market. A number of them, plus Synopsys, contributed to this forecast.

New Markets for EDA

EDA grows by solving new problems as discontinuities occur and design cannot proceed as usual. Occasionally discontinuities create new markets for the industry.

IoT Cookbook: Analog and Digital Fusion Bus Recipe

Experts from ARM, Mathworks, Cadence, Synopsys, Analog Devices, Atrenta, Hillcrest Labs and STMicroelectronics cook-up ways to integrate analog with IoT buses.

Is Hardware Really That Much Different From Software?

When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts from ARM, Jama Software and Imec propose the answers.

Hot Trends for 2015

System Companies are changes in development methods will be more obvious in 2015 together with higher percentages of mixed/signals designs.

EDA in 2015: Something New and Something Old

Projections for 2015 were deep in content and large in volume. Thus a series of articles had to be created. Read all of them in the next three days.

Is Hardware Really That Much Different From Software

When is hardware really software? Are software flows less complex? Are hardware tools less up-to-date? ARM, Jama Software and Imec experts propose the answers.

From Data to Information to Knowledge

Computers are good at manipulating data, and even to generate information. But computers have yet to acquire knowledge from what they process. Knowledge generating systems should be the next goal.

Review of Jama, ARM Techcon and TSMC OIP Shows

October issues of the "Silicon Valley High-Tech Traveler Log" - with Sean O'Kane and John Blyler - Highlights from TSMC OIP, ARM Techcon and Jama Software events.

ARM TechCon Videos: Interview with Ian Drew (Part 2: 'mbedding' the IoT)

Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 2, the guys discuss: ARM's mbed/mbed OS and Cortex-M7; the easy path to the IoT is made easy by ARM's new mbed environment. As well, Ian talks about heterogeneous cores and securing the IoT.

ARM TechCon Videos: Interview with Ian Drew (Part 1: Servers)

Embedded editor Chris Ciufo chats with Ian Drew, CMO, ARM. ARM's move into 64-bit servers with HP's recent “Moonshot” announcement; how the IoT grows from the enterprise and handsets; and ARM partners' complete infrastructure for servers.

High Power Tools for Low Power

An interview with Krishna Balachandran, product marketing director for low power at Cadence makes me focus on software quality.

Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design

One of the toughest challenges in the implementation of any processors is balancing the need for the highest performance with the conflicting demands for lowest possible power and area. Inevitably, there is a tradeoff between power, performance, and area (PPA). This paper examines two unique challenges for design automation methodologies in the new ARM®Cortex®-M processor.

Cortex-M processor Family at the Heart of IoT Systems

ARM's Cortex®-M7 provides performance and low power to IoT applications

This is not your father's MCU

The Cortex-M7 is really an extension of the Cortex-M4… designed for endpoints in automotive, Internet of Things and portable medical applications that will be expected to deliver 30 years’ of operation.

The Lanza's Challenge

Lucio Lanza is the 2014 Phil Kaufman award recipient. Our conversation shows how brilliant Dr. Lanza is.

The Divorce That Never Happened

ARM and Synopsys announce a multi-year agreement just in time for ARM TechCon.

Low Power Is The Norm, Not The Exception

Low Power Design is now the main stream in IC development. There is no more a separation between plugged-in circuits and battery powered devices.

Correct by Construction

Using IP Subsystems is a way to generate "Correct by Construction" portions of your IC.

What Is Not Testable Is Not Fixable

DFT is a key component of IC design. The technology is evolving to include architecture and algorithms development. Standards play a key role as well.

3D-IC's Are the Future

Designers need to design in true 3D, not just stack dies on top of each other.

Deeper Dive-Imagination promises a game-changer for multi-core design

In a recent announcement, Imagination Technologies introduced the first IP cores to combine a 64bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing.

Supporting Education to Build the Future of EDA

Significant numbers of members of the EDA industry foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Soft (Hardware) and Software IP Rule the IoT

Will soft (hardware) and software IP dominate the IoT market? Experts from IPExtreme, Atmel, GarySmithEDA, Semico Research and Jama Software respond.

It Is Not About Moore's Law

Moore's Law is often taken improperly to describe something totally different. This is the case with Kevin Morris's recent article.

Deeper Dive - Intel's 14nm - August 29, 2014

Earlier this month, Intel announced details of the Core M processor microarchitecture, the first to be manufactured using 14nm.

Complexity of Mixed-signal Designs

The major constituent of system complexity today is the integration of computing with mechanical and human interfaces. Both of these are analog in nature, so designing mixed-signal systems is a necessity. The entire semiconductor chain is impacted by this requirement.

Deeper Dive - Graphene Research - Aug. 27 2014

Recent research on the behavior of bilayer graphene brings scientists at Aarhus University, Denmark and the UK’s Science and Technology Facilities Council (STFC) closer to using grapheme in transistors, and other, alternative energy devices, writes Caroline Hayes, Senior Editor.

Intel's FinFETs and Professor Asenov's Independent Work

Weekly Chip-Science Highlights - Aug. 15th

The Intricate Puzzle Known as Chip Design

Newer Processes Raise ESL Issues

Leaving the solution to design and integration problems to a later stage of the development process creates more complexity since the network impacted is much larger. Each node in the architecture is now a collection of components and primitive electronic elements that dilute and thus hide the intended functional architecture.

The Entropy of EDA Tools

Deeper Dive - A 3D-IC round table - part II

What’s needed for 3D-ICs to flourish? asks Caroline Hayes, senior editor. Experts from Mentor Graphics, Altera and Synopsys have some ideas for future progress.

Deeper Dive - 3D-IC Part 1 Fri. July 11 2014

As the industry transitions from 2.5D to 3D-ICs, Caroline Hayes, senior editor, asked experts from Mentor Graphics, Altera and Synopsys for their view on what system designers need to consider in implementing 3D-ICs.

Deeper Dive - IoT Security

With new roles, IoT security will become even more important. Caroline Hayes, Senior Editor, asked Steve Kester, Shantnu Sharma (both AMD), Rich Rejmaniak (Mentor Graphics) and Rob Coombs (ARM) what is needed and how a secure IoT can be achieved.

Accellera Systems Initiative UVM 1.2

An Eclectic DAC

The type of exhibitors at this year's DAC 2014 was more varied than in previous year.


Our Day at DAC – Day 2 (Tuesday)

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the Chip Design editorial staff covering DAC 2014.

Our Day at DAC - Day 1 (Monday)

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the editorial staff covering "Day 1" at DAC 2014 - John Blyler, Gabe Moretti and Hamilton Carter.

Power management and IP

First half day at DAC. It is busier than I expected, but not as well covered by TV as Apple's Developers Forum.

Changing EDA-IP Relationships

Who is really your customer? Competitor? Well-known EDA analyst Gary Smith forecasts the future.

Why IP Providers Need the New 1149.1/JTAG

Intellitech's CEO CJ Clark explains why the latest JTAG update brings much needed capabilities to IP providers and IC developers alike.

Deeper Dive - Is IP reuse good or bad?

Caroline Hayes, Senior Editor asked four industry experts, Carsten Elgert, Product Marketing Director, IPG (IP Group), Cadence, Tom Feist, Senior Marketing Director, Design Methodology (TF), Xilinx, Dave Tokic, Senior Director, Partner Ecosystems and Alliances, Xilinx, and Warren Savage, President and CEO, IPextreme (WS) about the pros and cons of IP reuse versus in-house IP.

IP Integration to accelerate SoCs

As the accelerating market of SoCs inevitably means a faster rate of adoption, system level designers are also faced with fragmenting markets, with new standards adopted and with multiple types of complex requirements in a system. The integration of IP (Intellectual Property) can be a boon, but there are caveats, as Caroline Hayes, Senior Editor reports.

The IP business: on the cusp of another evolution?

The IP business started in the late 1980's and early 1990's with the availability of synthesis. ARM in England, HDL Systems in the US, and Synopsys were the first companies to offer IP products. Now, although still in need of some improvements, the IP industry is a multi-billion industry that continues to grow.

Passion Project for Engineers

Engineers are a creative bunch but what are their passions outside of work? You might be surprised.

Brilliant Blunders: From Darwin to Einstein

Drawing on the lives of five renowned scientists, Mario Livio shows how even these geniuses made major mistakes and how their errors were an essential part of the process of achieving scientific breakthroughs. Dr. Livio was interviewed by John Blyler, Chief Content Officer at Extension Media.

The Road to 1 Million Tapeouts

When Cadence Senior Vice President Martin Lund uttered those words with a smile on his face, the small crowd at an industry event here chuckled knowingly.

Insights from the Sci-Fi Community on Wearables

Several recent interviews with technical experts about trends in wearable technology made me wonder how sci-fi writers might envision for the future.

Imec's mm Wave Motion Sensing Technology

Motion sensing applications with mm wave technology at Imec is the topic of this interview between Liesbet Van der Perre, Imec Program Director of Wireless Communication, and John Blyler, VP and CCO at Extension Media.

Keeping upstream with video content

The quadrupling of resolution in 4k video opens up broadcast, gaming and other sectors to a world of mobility via the ubiquitous smartphone. By Caroline Hayes, Senior Editor.

Behavioral, Legal, Political Issues of Internet of Things

If it were possible to adapt humans to the wonders of technology in a positive manner, the world would certainly be better. But reality says that instead humans adapt technology to their own interest, not the other way around.

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures is raging in all spaces, from deeply embedded through mobile to servers. Choosing the right ecosystem partners is crucially important.

Xpedition Awaits for PCB Designers

Mentor Graphics announces improvements to and the re-branding of its well-known Expedition line of printed circuit board (PCB) design and manufacturing tools.

DVCon Europe Is The Wrong Venue

Accellera Systems Initiative has announced the first European DVCon conference to be held this October 14 - 15 in Munich Germany. I believe this is a suboptimal choice.

The Wheels of Industry Roll On

The wheels of industry roll on. Themes at Embedded World in Nuremberg were predictable, with automotive, industrial automation and IoT but there were some twists and revelations too.

System Level Power Budgeting

The challenge is to find ways to abstract with reasonable accuracy for different types of IP and different loads. Reasonable methods to parameterize power have been found for single and multiple processor systems, but not for more general heterogeneous systems.

In Focus - System News for Feb. 2014

Shannon covers the last news in the semiconductor systems engineering industry and research developments for February 2014. This month's highlights include the paper brain, MEMS and IEEE on Internet-of-Things (IoT) standards, Da Vinci themed design competition, and IoT at Embedded World.

ISSCC: Perspectives on System-Design Evolution

Recently, the annual ISSCC conference took place in San Francisco, where researchers from around the globe share insights into circuit- and system-design breakthroughs.

Starting A New EDA Company

If you want to start a new successful EDA company look at the system level. Develop hardware and software components and the tools to assemble them together with third party proprietary components into a leading edge system.

Deeper Dive - Software Attacks

In response to security vulnerabilities, system level designers have made the security of data and content a prime objective in our connected lives

Security Challenges in a Connected World

One of the joys of today’s electronics devices is that they are connected. However connectivity and sharing files can make a system vulnerable.

High Level Synthesis (HLS) Splits EDA Market

Recent acquisitions and spin-offs by the major electronic design automation company’s reveals key differences in the design of complex chips.

Nanotechnology Transforming Material Civilization

What are the implications of atomically precise manufacturing on today's lithography-based semiconductor fabrication? Dr. Eric Drexler from the Oxford Martin Programme at the University of Oxford talks about these issues during an interview conducted by John Blyler, Chief Content Officer at Extension Media. This interview occurred at the FEI offices in Portland, OR, prior to Dr. Drexler's lecture at the Institute for Science, Engineering and Public Policy (ISEPP) monthly event.

Target Breach Highlights IP Indifference

The good news is that large amounts of IP go into the design of smart-card chips and RFID tags. The bad news is that the general public isn’t really interested.

The Rise of Application-Driven Design and the Move Beyond EDA

Moving beyond EDA with the rise of application-driven system design.

Sensor and Instrumentation Issues for the Indy Race Cars

Interview with Warren Wilson, Damper Engineer for KV Racing, during the August 2013 Indy car race at Sonoma Raceway. Wilson talked about the instrumentation challenges for the tire and shock subsystems on the race cars.

Automotive HW-SW Integration - SAE Event at UofW Campus

How do automotive electronic designers and testers handle the complexities of hardware-software integration at the chip, board, and network levels?

Deeper Dive - Graphics Processing

Whether in tablets, wearable fitness devices or huge infotainment screens, graphics plays an important role - but there are considerations and challenges to be met.

John's and Sean's ChipEstimate.TV Travel Log

Highlights from the IEF event in Dublin, Ireland and Imec's technology forum in Leuven, Brussels.

Integrating Sensors and Selecting Processors

How do designers deal with analog sensor design and the resulting data algorithms? Has the emerging world of IoT changed the way that processors are selected?

Imagination Tech's Tony King-Smith talks about IP, verticalization and products.

This video is about ImagTech_Tony-King-Smith

Mentor's Wally Rhines - Learning Curve; Golden 28nm, IoT Innovation and Systems Engineering

Wally Rhines, Chairman and CEO of Mentor Graphics, talks about Moore's Law in light of the Learning Curve; 28nm as the golden node; critical need for IoT innovations; and why systems engineering often fails.

Connected Key and Freescale IoT at ARM Tech Con

ARM connected keg hardware and application software demonstration provides a great segway into Freescale’s IoT exhibit.

Stretchable Circuits Go Blue

Here's a short clip about the Imec's stretchable, organic circuits. One potential application of this low-level light therapy (LLT) treatment for wrist Repetitive Strain Injury (RSI) or as a jaundice blanket for new born infants. The RSI application is being developed with Philips as part of the EU Project Place-It.


John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.

Electronics: Change Is In The Air

The electronics industry is on a verge of a drastic change, and with it EDA and to a lesser extent the semiconductors industry will have to change as well. EUV processes will require close collaboration among designers, EDA vendors, and foundries in order to adapt a design implementation to the specific characteristics of a foundry process.

ARM TechCon, Semico Research IP Impact, and the MEMS Congress

Here are my quick thoughts from several recent shows that covered everything from IoT and software to semiconductor IP and MEMS take-overs.

What’s shaping the modeling environment?

Increased complexity is not so much a challenge as an impetus, as Cadence, Mentor and National Instruments discuss the trends in model driven development.

Will a New DSP-based IP Subsystem Emerge from Rumors?

Two rumors about Qualcomm, Arteris, and DSP architectures lead to tantalizing speculation about a new type of DSP-based IP subsystem.

Deeper Dive - IPextreme Blows Hot for ColdFire

There is a shift occurring in the semiconductor market, driven by the consumer space, believes Warren Savage, president and CEO, IPextreme.

History Lesson from Acorn to ARM for IoT

Thinking about embedded design for the Internet-of-Things invokes processors from the past, like the 6502 and ARM's predecessor, the Acorn’s BBC Micro.

Accellera Systems Initiative Continues to Grow

Accellera System Initiative continues to grow in size and importance within the electronics industry.

Combining the Linux Device Tree and Kernel Image for ARM

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel and its various artifacts into memory for ARM virtual platforms. The first was A SystemC TLM 2.0 ARM ...

ARM's Embedded Strategiest Talks about the IoT

Extension Media's John Blyler interviews ARM's Embedded Strategist, Dominic Pajak, about the Internet-of-Things.

Complexity Spreading vs. Intelligent Embedded in the IoT

Which phrase is more indicative of the Internet-of-Things (IoT) depends upon your viewpoint – namely, from the process or the products.

Flashback to June 2000: "Are Mobile Communication and Computer RF Technologies on a Collision Course?"

The interoperability of multimode RF communications systems and multi-protocol mobile-computing devices will require a future convergence.

What Powers the IoT?

Gartner analyst Stephan Orr gives an early look at a major research report in energy harvesting and low power semiconductors designs for the IoT market.

Mixed Signal and Microcontrollers Enable IoT

Analog and digital designers must embrace new levels of closeness in the Internet-of-Things (IoTs). Will complexity spreading be the ultimate challenge?

Software-Hardware Integration of Automotive Electronics

My SAE book arranges and extrapolates on expert papers in automotive hardware-software electronic integration at the chip, package, and network vehicle levels.

ESL Market Potential

The bad new is that the electronic system level (ESL) segment of the EDA market still needs more robust standards. What's the good news?

NIST Is Closed - Try the French Government

A casual Google search on nanotechnology results in embarrassment over the unnecessary US shutdown and a desire for French croissants.

Results from the RF and Analog/Mixed-Signal (AMS) IC Survey

A summary of the results of a survey for developers of products in RF and analog/mixed-signal (AMS) ICs.

Experts Roundtable: Design-for-Test

System-Engineered Design discusses the evolution and future of design for test (DFT) with Synopsys, OptimalTest, Mentor Graphics and Cadence Design Systems.

Mixing it up in Mixed-Signal Test

The balancing act of system level verification and test becomes more complex as analog IP grows with more digital control logic.

What is the current state of ESL tools?

Electronic System-Level (ESL) design is a dynamic process but will it adapt to the changing requirements of complex IC and higher systems?

A Web of Security for Medical Devices

John Travel adventures from Hot Chips and Beyond

HOT CHIPS has been known as one of the semiconductor industry's leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August on the Stanford University campus in the center of the world's capital of electronics activity, Silicon Valley. John Blyler, VP, Chief Content Officer, Extension Media

Getting a Bead on the Bad Guys

Security Is What You Make of It

End of an embedded era: Emerson De-”Mots” Motorola Embedded

Emerson today announced plans to sell 51 percent of Emerson Network Power to Platinum Equity for $300 million. It’s a shame, for sure. But what’s equally interesting are the embedded technologies and their creators leaving the Emerson camp, and how we got to this place.

Sweet New Android Versions Still Leave Room for Embedded Linux

From SEMICON West 2013: Luc Van den hove of imec

Crossing interdisciplinary boundaries, 3D stacked die collaboration, open innovation and IP challenges were the topics of an Imec interview at Semicon West.

PICMG Picks Up Steam—All the Way to the Red Planet

PICMG President and Chairman Joe Pavlat describes PICMG evolutions from small to large, including COM Express, CompactPCI, AdvancedTCA and MicroTCA.

Does Altera Have “Big Data” Communications on the Brain?

In wireless, wireline and financial big-data applications, moving all those packets needs prodigious FPGA resources, not all of which Altera had before its recent series of acquisitions, partnerships and otherwise wheeling-and-dealing.

MEMS Industry Group's Karen Lightman Raps about Cool Apps

MEMS and smart-fusion technologies are cool, enabling Google Glass, energy harvesters, wine sniffing, and other apps. Come see for yourself at the MEMS Executive Congress.

Is IP Theft the Leading Cause of Tech Decline in the US?

A recent Financial Times (FT) article doesn't mince words in calling China’s “international theft of inventions part of a national business model.”

3D Printing vs. Semiconductor Parallelization

A perceptive engineer challenges the suggestion that an army of 3D printers may one day replace portions of the semiconductor wafer and chip industry.

What’s Your Favorite COTS Technology?

Automotive Ethernet Moves to the Fast Lane

Augmented Tools Design Reality

Augmented reality appears in consumer applications and virtual-prototyping designs for the early validation of everything from tablets to refrigerators.

PCI-SIG-nificant Changes Brewing in Mobile and Small form Factor Designs

Can We “Tock”? Intel’s 4th Generation Core Haswell Targets Embedded, Big Time

USB Lets Power Go to its Head

Intel Maintains its ATCA Foothold

DAC 2013 Pictures

M2M Hits the Road (and Rails)

AMD’s Single-Chip Embedded SoC: Upward and to the Right

“Mirror, Mira”: IVI vs. Smartphone

The biggest question faced by every auto manufacturer is this: in-car native system or rely on smartphone apps?

DAC – Video Latency; Platform as a Service; 262626; and ARM-12

My Tuesday at DAC involved CAST IP, Mentor Graphics, Dassault Systemes,, and Globalfoundries-ARM.

Dr. Stan Krolikoski’s Words and Award

A look back at Stan’s blogs and a look forward to his award.

Gary Smith’s Sunday Night, Pre-DAC Forecast

Building on last year’s multi-platform design focus, EDA luminary Gary Smith busts the myth of the $170M SoC design cost.

More MEMS Integration: Into Sensors, Systems, and Humans

Humans will touch, move and interact with MEMS as part of the exploding Internet of Things.

MEMS Get Smarter, Making Developers’ Jobs Tougher

Long Standards, Twinkie IP, Macro Trends, and Patent Trolls

In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values, macro trends, and changes wrought by patent trolls.

Getting ARM’d for Innovation in x86 Modules is a Power Play

Supply Chains, Big Data, and Point-of-Sale for EDA and IP

These issues were addressed by supply-chain, product-lifecycle-management, board-design, and chip-design services companies.

HTML5 Is What’s Needed To Rapidly Develop IVI Automotive Apps

Is HTML5 the right answer for the rabid consumer’s taste for car tech, while still giving the auto manufacturer the safety and security they’re required to offer by law?

IP Smoke Testing, PSI5 Sensors, and Security Tagging

The growth of semiconductor IP brings challenges for subsystem verification, integration, security, and the addition of sensor standards. Can Savage clear the smoke?

ISEPP: The Hunt for Earth 2 - A Shower of Kepler Planets!

Editorial Director John Blyler interviews Dr. Gibor Bari of the University of California - Berkeley (interview done on March 8, 2013) about the hunt for Earth-like planets in our galaxy.

Mobile Device Power-Management Strategies

Consumers’ love affair with always-available mobile devices shows no signs of waning. But as reliance on these devices grows, innovative power management can be a significant product differentiator. We talked to Evan Schulz, applications engineer for microcontroller products at Silicon Labs and Pradhyum Ramkumar, product marketing manager for MSP430 ultra-low power micro-controllers at Texas Instruments to get their advice on a range of new approaches.

Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress

What do all of these things have in common? They were key topics addressed by Cadence, Samsung, and others at CDNLive 2013.

M2M Promises Growth for Embedded, Wireless, Sensors, and More

The machine-to-machine (M2M) phenomenon is accelerating and is coming to just about any connected technology near you.

Power Drives MCU Evolution

Requirements for portable, low-power consumer devices, as well as energy-efficient embedded systems, drive MCU development and offer options for embedded engineers.

Semiconductor Leaders Respond at Common Platform Technology Q&A

Will EUV ever be ready? What about nanotubes? When will Moore's Law end? These questions were answered at the recent Common Platform Technology's press Q&A.

Flexible Yogurt-Lid Electronics Become a Reality

Truly flexible electronics from processor, memory, interface, and battery components are here, thanks to IBM, STMicro, Leti, Imec, Kaist, Kovio, and others.

Surprises Abound As Subsystem IP Gains Prominence

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation.

Semiconductor Growth Turns Wireless

2013 Trends: New Standards, Lower Power, and Rugged

The military’s infatuation with SWaP-C begins to drive non-defense suppliers as myriad markets and applications need better-than-commercial.

Designcon 2013 Videos with AWR, Agilent, and More

IP Insider's John Blyler and Chipestimate.TV's Sean O’Kane interview AWR (National Instruments) and Agilent and talk about cool technology.

Cameras “See” More with Imec Hyperspectral Imaging

New CMOS-based imagers offer smaller size and cost, but with greater discriminating powers over today’s RGB-based cameras.

VME’s Long From Dead; Destined To Co-Exist With VPX And Serial Fabrics

A discussion with Aitech and Curtiss-Wright about heat, processors, fabrics, and VME’s synergy with VPX and all things “U”.

Changes In The Supply Chain

Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it.

Inside The System-Level Supply Chain

System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation.

9 Issues Face Today’s Semiconductor Supply Chain

While the GSA report focuses on China, the challenges discussed apply to the global IC supply-chain market.

Fundamental Laws of (FPGA) Nature: Similar, Yet Different

Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.

Tizen OS for Smartphones – Intel’s Biggest Bet Yet

Modular FinFET Increases Planar-to-Non-Planar IP Reuse

At IEDM, Globalfoundries explained why its 14-nm-class Fin with a 20-nm back-end combination would increase planar IP portability to non-planar FinFETs.

MEMS Goes Mainstream

Choices on the best way to combine MEMS and electronics are being driven by the cost, size and performance requirements of the consumer electronics market, and there are tradeoffs involved in each approach

Chinese Embedded-Design Contest Offers Insight

Reviewing the list of first-, second, and third-place winners reveals the technology direction of China’s university/industrial embedded-development community.

STMicroelectronics Pushes SOI While Leaving the Mobile Space

Why is one of Europe’s leading semiconductor IDMs pushing into leading-edge, 28-nm FD-SOI technology while leaving a market where such technology might be useful?

The Current State Of Model-Driven Engineering

Panelists from industry, national laboratories, and the Portland State System Engineering graduate program recently gathered for an open forum on model-driven engineering.

Model-Driven Development Is Key to Low Power

Mentor Graphics explains why the model is the design at a system-engineering forum hosted by Portland State University (PSU), INCOSE, and the IEEE.

Semiconductor GPU IP Faces Cloud Division

Cloud computing offers many challenges including the division of graphic-processing IP and rendering tasks between the mobile device and cloud-based servers.

System Simulation Moves from Goods and Services to Experiences

This is the first of two stories about Dassault Systemes move into the world of semiconductor development.

Chip Design Enters the Third Dimension

How will stacked die affect the IP supply chain? FinFet transistor structures will require new Spice models. But what else?

Cloudwashing – A Rose by any Other Name

The white-washing of cloud computing remind us of the evolution of decades old rightsizing and client-server technologies.

Software Developers Benefit from Windows 8 Hygiene

A new level of hardware and software IP integration is needed for true power optimization.

Virtual Reality for Chip Design?

As chip design moves into the realm of 3D transistor structures and even MEMS, virtual reality simulators may prove a necessity for both architects and educators.

What Drives ASIC Prototyping with FPGAs in 2012 and Beyond?

The latest results from the annual CDT survey point to changes in the reasons behind ASIC prototyping – from hardware, software, and systems to IP.

Hot Chips, Si IPOs, Wright’s Law and Desert Spaceports

John and Sean talk about the Hot Chips show, the decline of Silicon IPOs, Wright vs. Moore’s Law, and spaceports in the desert.

IDF 2012 Shifts Focus to Cloud and Mobility

A wide range of processor types from datacenter to smartphones should enable the accelerated growth of software applications for Intel-based devices.

Datapath Designs, Near Threshold Voltages, and Deeply Depleted Channels

What do these tongue-twisting technical phrases have in common? They were all part of the morning session on the last day of the Hot Chips forum.

Tweets from Hot Chips

Check out my Tweets from the recent Hot Chips forum!

“Dies Caniculares” Reading List

This “Dog Days” of summer technology list is not to be read indoors!

Hardware-Software Tops Priority List For ASIC Prototypers

The most important decision facing chip prototyping designers this year (2012) concerned the completeness of the combined hardware and software platform. (See Fig. 1). Cost and boot time followed as the next most importance issues. Close to 200 qualified respondents participated in the annual Chip Design Trends (CDT), “ASIC/ASSP Prototyping with FPGAs” survey.

System Realization And the X-51A Failure

NASA’s latest X-series experimental aircraft – the X-51A – failed due to a familiar control-fin problem. But is poor system integration also to blame?

Many Cores but Little Parallelism

Has the move to thin and light mobile devices sidetracked the much hyped rise of parallel coding programs for many-core chips?

Analog and RF Added To IC Simulation Discussion

System-Level Design sat down with Nicolas Williams, Tanner EDA’s director of product management, to talk about trends in analog and RF chip design.

Semicon West 2012 Videos

Show floor interviews with leaders from Semico Research, MEMS Industry Group, ASML, Soitec, Applied Materials, and IMEC.

Software Entrepreneur Helps Guide EDA Giant

Cadence’s Jim Ready, founder of MontaVista, tries to bridge the software understanding gap between EDA designers versus embedded-application developers.

DAC 2012 Retrospective Video

Another excellent Design Automation Conference (DAC) 2012 video collage from the pros at Chipestimate.TV.

SOI Parity with CMOS Good News for IP Designers

Soitec panel at Semicon West challenges both the IDM model and the dominance of bulk CMOS as material of choice for chips at 20 nm process nodes.

Semiconductor’s Sustainability Promise

The Imec-Semi keynote highlighted how the semiconductor collaboration model and technical advances are addressing critical world issues.

Wearable electronics; Semiconductor expertise destroys bacteria; Top IP scorer; Trolls don’t help inventors

So much came to light this week that I can only offer a sampling from each topic.

End of Contributed Content is Near

Legal efforts by major technology companies are removing all incentives for reputable publishers to run contributed content. But will anyone care?

Nano-technology in a Macro-world

Imec, Belgium’s R&D leader, will join with global partners at Semicon West to showcase nanotechnology advances in almost every imaginable market.

Intelligent Embedded Systems elude Definition

Although a boon to semiconductor sensor, analog and RF-wireless IP providers, few practitioners seem able to clearly define intelligent embedded systems.

New Kinds Of Hybrid Chips

Crack open any SoC today and it will contain a variety of third-party memory, processor cores, internally and externally developed software and analog. In fact, the main challenge of most chip designs today is integration and software development rather than developing the chip from scratch.

Goodbye BIOS – Hello UEFI

Efforts to modernize traditional PC boot firmware leads to Intel’s collaboration with Phoenix Technologies on UEFI BIOS client and server development.

Annual "ASIC Prototyping with FPGAs" survey

There’s still time to win a $15 Amazon gift card by completing a short survey on “ASIC Prototyping with FPGAs.”

What Color is Your Semiconductor IP Box?

Black, white and even grey box testing techniques from the world of hardware and software integration are finding a place in semiconductor IP subsystems.

Images of Day 3 at DAC 2012

Day 3 of DAC, captured in pictures and captions.

Images of Day 2 at DAC

Day 2 of DAC, captured in pictures and captions.

Systems, Software and IP Merge at DAC

Day 1 of the 2012 Design Automation Conference (DAC) captured in pictures and captions.

ASIC/ASSP Prototyping-Verification with FPGA 2012 Survey

Participate in the (2012) annual Chip Design "ASIC/ASSP Prototyping-Verification with FPGA" survey and win an Amazon gift card!

SoC Costs Cut by Multi-Platform Design

Upward SoC cost trend blunted as designers reused software, verified IP and fewer blocks, reports long-time EDA analyst Gary Smith.

Points-of-Interest in the "DAC Zone"

If I had my choice, these are the papers and events that I would attend at the upcoming Deign Automation Conference (DAC).

Rethinking SoC Architectures

Virtualization and coherency, two concepts that can trace their origins back several decades, are suddenly gaining attention these days—but for entirely different reasons and uses.

Trends In Analog And RF IC Simulation

System-Level Design (SLD) sat down to discuss trends in analog and RF integrated circuit design with Ravi Subramanian, president and CEO of Berkeley Design Automation, (at the recent GlobalPress eSummit) and later with Trent McConaghy, Solido’s CTO. What follows are excerpts of those talks.

Does Innovation Lie Beyond Software?

Today, it is fashionable to suggest that innovation lies beyond what is common. But perhaps innovation lies in seeing the familiar in a new way.

Print’s role in Semiconductor IP Design

Print content continues its steady decline in our everyday lives. But what is the real impact on semiconductor IP designs?

DDM and PLM Tools Challenge Semiconductor IP Reuse

Recent data suggests the value and shortcomings of design data management (DDM) and project lifecycle management (PLM) tools to improve IP reuse.

Low-Power Undercurrents at GlobalPress 2012

While not the primary theme at this year’s Globalpress eSummit 2012, low power concerns were present in almost every presentation as these snippets reveal.

Google’s Software Process Challenges Semiconductor IP

A recent FCC report blames Google’s software development process for its WiFi privacy breach. How stable is the process for semiconductor IP creation?

Grenoble IP Cluster Grows into Embedded

The French technology center fosters growth through hardware-software integration while sharing technical IP, business and marketing expenses.

Interview with Globalfoundries about AMD-ATI

John Blyler, editor-in-chief for Chip Design magazine, interviews Mike Noonen, Sr. VP of Worldwide Sales and Marketing at GLOBALFOUNDRIES during the Common Platform Technology Forum 2012 (courtesy TV).

Social and Mobile Players Change the Game

The rise of the social, mobile Alpha-Influencers segment opens new horizons for the game-related technology and content-services industries.

Game Over? – IP beyond Moore’s Law

Will the creation of a repeatable, single-atom transistor mean the end of Moore’s Law and IP as we know it?

Wireless IP Grows in Surprising Ways

While growing, analog and wireless IP usage may face challenges in manufacturing preferences at lower nodes and emerging LTE technology trends.

JohnB's Tech Bits

More SI, Less EDA at DesignCon 2012

This year’s DesignCon show focused more on board-level signal intregity and testing issue than on chip design and verification.

Venture Capitalists see Major Investing Changes

At the recent AO Venture Summit,Silicon Valleyinvestors cautioned about changes to traditional investment funding models as the semiconductor market enters a cyclical downturn.

Carbon's Exchange Bolsters Front-end IP Chain

Today’s announcement of Carbon’s IP Exchange portal provides evidence of the growing importance of the semiconductor IP design-manufacturing chain.

IP Trumps Moore’s Law in SoC Costs

Apple continues to reduce system costs through customized chip design via IP integration and software tailoring, not through traditional cost per gate.

Time Cloak for Digital Logic?

Quantum phenomena can be view as waves or particles. Time cloaking has been demonstrated with waves. What might that mean to electron flow for circuit designers?

APAC Surges Ahead in Global IP Market

A recent report by Technavio Insights confirms strong growth in IP usage and development in Asian countries. What will this mean to the future of chip design?

Technical Trade-offs Leave Long Tail

Architectural trade-offs – typically resulting in IP – made early in a design can affect a company’s market participation for years to come.

RF Telescope at Arecibo Picks up Dr. Who

Yes - it's a fake story. Still, it would be interesting to see the mathematics showing the reflected signal strength from 25 light years away.

Voltage Spikes Lead to Deeper Integration

The move by Silicon Labs toward power systems integration on MCUs points to a larger trend followed by Silicon Blue and IMEC, among others.

Conservation of Design Pain

Regardless of system-design approach, painful tradeoffs are still needed--usually during integration.

Memory Challenges In The Extreme

Next to computation, memory is the most important function in any electronic design. Both processor and memory devices must share the limited resources of power and performance. The relative weighting of these tightly coupled constraints varies depending upon the application.

IP Developers Will Play Games

Gamification is moving from social media networks to technical sites for both motivational and generational reasons. Engineers will have to play to win.

Commoditization Ghetto? Or a Study in Semantics?

Call it what you will, commoditization is not a welcomed word in the EDA, IP or electronic hardware communities.

Technology Gives Way to Spooky Readings

Alright – I admit it! Last night wasn’t spent working on story about silicon manufacturing variability below 20nm. Instead, I snuck out with my better half and attended ... must I confess? A poetry reading!

Jobs, Ritchie and America’s Media Obsession

Two deaths this week reinforceAmerica’s media obsession with marketing over engineering. One death is heralded as the passing of a demigod (Steve Jobs), while the other received obscurity (Dennis Ritchie).

System Dictates Transistor Design

It is easy to miss the connection between advances in transistor architectures and the relationship to the larger system. How do improvements in transistor development fit into the big picture?

When A Physicist Comes Knocking

Will neutrinos from a supernova in the Tarantula Nebula save Einstein endangered postulate? Does all research have to be immediately profitable? Will collisions at Fermilab’s Tevatron slow the speed of declining scientific prominence in the United States?

Proprietary On-Chip Connections Yield To NoC Designs

Interconnect technologies are nothing new at Intel. During the recent Intel Developers Forum (IDF) 2011, several processor-centric interconnect technologies were on display in the company’s Labs Pavilion. Most noticeable of these were Many Core Application Research Community (MARC) and its derivative called the Many Integrated Cores (MIC) projects.

What do Medical Devices, Facial Recognition, Genivi, and Clustering Processors have in Common?

All of these very cool technologies - showcased by Intel’s ECA partners at IDF2011 – provide a clear direction for future trends in medical, automotive, and consumer electronics.

Pictures from Intel Developers Forum (IDF) 2011

Lower Consumer Power Trend Masks Manufacturing Component

Does a drop in residential power usage – thanks in part to lower power semiconductor devices – really mean that the world is becoming energy efficient or does it hide manufacturing energy costs?

Engineering – The Lost Profession

I just finished reading “The Lost Symbol,” by Dan Brown. It was about the misunderstood meaning and purpose of the Masonic Order. A similar story could be written about the profession of engineering.

Robot Obeys With The Wave Of A Hand

Both the sensor and wireless market continue to be strong growth areas in the electronics industry, especially the mobile segment. This growth is attributed in large measure to the cost-effective availability of sensors based on microelectromechanical systems (MEMS) and RF components.

CEO’s Debate Design at Upcoming GTC 2011

Following the industry trend toward smaller but more focused shows, Globalfoundries August 30th event promises a lively discussion as semiconductor leaders wrestle over the future of chip design.

Time Travel is Out: Stopping Time is In

Time travel is fascinating, but passé. Instead of travel, how about the antithesis, namely, not traveling? It’s like a Zen moment without the moment. Is time flowing or stopped?

Connectiveness May Harm Hardware Trade Shows

Increased mobile connectivity by show attendees may cause fearful hardware vendors to withdraw from or at least remove their equipment from leading B2B trade shows.

Semi Inventories Rise, Expansion Slows

Two recent reports suggest that the semiconductor industry may be headed for slower growth throughout the last half of 2011.

Blacker Boxes Lie Ahead

Few pundits have addressed the system engineering development implications of the recent EDA and semiconductor company’s move toward platforms that include both chip hardware with associated firmware software.

Mobile Markets Bode Well for OTP Memory

Analyst reports from IHS iSuppli suggest a strong market for NAND and DRAM memories, which will be good news to related non-volatile memory devices such as one-time programmable technologies.

IP’s Silent Presence in Automotive Market

Even though there was no specific mention of IP at this year’s Integrated Electrical Solutions Forum (IESF), all discussions about the future growth of both infotainment systems and self-braking, parking and driving autonomous vehicle operations will only be possible by a heavy reliance on chip and FPGA IP.

DAC Hits for Tuesday!

DAC Hits for Monday!

There is so much to cover at DAC, but so little time to cover it. Below are my highlights for Monday (6/6).

John Blyler Reports on Sunday Night!

Growth will be slow unless EDA vendors can slash the cost of developing chips; re-use and stacking are leading options.

EDA Inflections On Technology Innovation

Everyone talks about innovation. Start-up companies are the most visible vehicle for innovation, but also the most risky with a 1-in-10 chance of modest success. Less visible is the innovation that constantly must occur in fully formed, large companies if they are to continue to succeed. System-Level Design (SLD) talked with the three major EDA companies about the challenges to innovation: Michael McNamara, vice president and general manager of system-level design at Cadence; Serge Lee, vice president and general manager of new ventures in the system-level engineering division of Mentor Graphics; and Michael Jackson, vice president of engineering for physical design at Synopsys.

Embedded Software Developers Need Their Space

Improvements to several IDEs should make life a bit easier for time-constrained, globally separated, and processor-centric embedded-software developers.

Impressions from ESC 2011

Here are my rough impressions from the last four days of attendance at the Embedded Systems Conference.

Impossible Astronaut and Supercomputers in the Desert

The premier of a science fiction favorite and the start of a supercomputing competition all take place in a landscape rich in secret labs and alien sightings.

R&D Focuses on Low Power and Stacked Die

Atrenta collaborated with the French laboratory CEA/LETI in a research and development effort to advance power reduction and 3D stacked die EDA tools.

Altium Pins Hopes on China

The Australian-based, electronic design software company is relocating its headquarters and core R&D expertise to Shanghai, China.

Mentor or EDA Industry – Who is to Blame?

Mentor’s woes with Carl Icahn may stem from a misunderstanding of the complicated EDA market rather than the company’s financial condition.

ATOM Leader Leaves Intel

Departure of Intel’s Senior VP and GM of the Ultra Mobility Group may cast doubt upon or show commitment to the company’s embedded mobile market strategy.

Carl Icahn’s Effect on Mentor Graphics

The short- and long-term effects caused by activist shareholders like Carl Icahn highlight the dangers of aquisitions based upon non-industry specific financial indicators without an understanding of the industry itself.

What Kakalios Got Right?

The author of "The Physics of Superheros" explains why the predictions of jet packs and flying cars pales in comparison to what science has really given us.

Icahn Offers $17/share for Mentor Graphic

President’s Trip to Intel

Icahn Seeks Mentor’s Acquisition or Sell-off

Is this proxy challenge a legitimate push for fiscal efficiency or yet another example of Wallstreet recklessness?

Nanometer Chips Blend Work on Quantum Affects and Light

Verification Moves To Forefront With Software And Methodology Focus

All chip designs need some level of verification. This need has created an ecosystem of verification intellectual property suppliers (VIP), SystemVerilog users, and integration and EDA interoperability tool companies. System-Level Design discussed these issues with Dennis Brophy, Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics; Thomas Anderson, group director, verification product management and Ran Avinun, marketing group director for system design and verification at Cadence Design Systems; Neill Mullinger, product manager for verification IP, Michael Sanie, director of verification marketing and Frank Schirrmeister, director of product marketing, system-level solutions at Synopsys. What follows are excerpts of those discussions.

ASIC and ASSP Prototypes Accelerate Below 65nm

2010 Survey data suggests a rapid increase in ASIC designs targeted below 65nm process node.

Collaboration Penalty Is Steep For Engineers

System-Level Design sat down to discuss chip-design productivity and quality issues with Srinath Anantharaman, president and founder of Cliosoft; Ronald Collett, president and CEO of Numetrics Management Systems; and Michel Tabusse, CEO and co-founder of Satin Technologies. What follows are excerpts of that discussion:

Human Intentions Affect Electronics

While Psyleron reveals the mysteries of quantum entanglement to an eager public, scientists remain silent for reasons that may surprise you.

"The Function of Form" Flashback

Back in the early ‘00s, I covered the latest in wearable wireless technology. Today, my Facebook friend and past colleague Nigel Ballard posted a blurb about an antenna made from seawater. I wonder if such an antenna could be coupled with a Wi-Fi woven swim suit? Of course, the swimmer would have to be out of the water for it to work.

Dark Energy’s Role in Cosmology and Semis

Distinguished Professor Alex Filippenko speaks about the role of dark energy and matter in the paradoxical expansion of our universe while hinting at potentially related challenges in quantum mechanics.

UFO vs. Ghost Hunters

A ballot initiative in Colorado has created a spirited debate between extraterrestrial believers and their ghostly brethren, both claiming that science and the least blurry pictures are on their side.

New Semiconductor Fab Comes to Oregon

Intel announces plans for a leading edge 22nm chip development facility in Oregon, while upgrading other manufacturing plants in the US.

Embedded Trends from IEEE OctoberBest

Much tighter integration between processors and FPGAs, growing IP issues, interface challenges, analog power management were the hot topics debated at this year’s panel event.

Why did Microsemi buy Actel?

Programmability seems to be the Holy Grail in today’s acquisition hungry world of hardware electronics as chip vendors partner with or buy up FGPA companies.

Lynguent, Altos, InPA and Faust in Copenhagen

My review for the week of Sep 6, 2010.

As Summer Ends, Events Begin

As August comes to an end, designers and manufacturers of the high tech world get ready to meet.

Simple Example Highlights Hardware-Software Tradeoff

Here's a simple example that shows the basic challenges engineers face when trying to implement a task in hardware vs. software.

Small Embedded Computing Show is Rich in Technical Tidbits

A local embedded systems show provided a great opportunity to learn about the technology behind the products.

OSCON Shows Breadth of Open Source Software

Touring the exhibit floor at O’Reilly’s Open Source Convention (OSCON) provides a glimpse into the variety of established companies, start-ups and non-profit groups that support the open source movement.

Mentor-Icahn and the Outside Acquisition of EDA

Natural business and technology breakpoints may be barriers between EDA and PLM-ERP buy-outs.

Mentor Graphics' Summer of Discontent

Like a Shakespearian play, every other summer seems to bring a new suitor for Mentor affections. The summer of 2010 is no different, though the stakes are getting higher.

Videos from DAC, E3 and Arecibo

Scalable Architectures Expand into FPGAs

Reusable IP to meet time-to-market and cost demands is the main driver.

What does Carl Icahn really want from Mentor?

Whether it is short term gain or long term growth, Mentor’s latest suitor will need a deep understanding of the EDA market and its players to be successful.

Weatherford - Test blog with Flickr in Preparation for DAC'10

Why Gamers Matter to DAC

Seemingly unrelated market may hold solution for flat attendance, rising exhibitor costs.

DAC Bloggers Reflect on Two Years of Change

Tumultuous changes in the economy and media landscape have muted many of the concerns between bloggers versus journalists, but differences remain. Does it matter?

Computational Powerhouse Hidden In Island Jungle

Perhaps one of the more unusual applications of serious computing power is innocuously located within the sweltering jungles of Puerto Rico. Inside a modern, air-conditioned data center in the Aeronomy Department of the Arecibo RF Telescope Observatory, scientists and engineers study the upper regions of the Earth’s atmosphere. Their goal is to help improve the reliability of radio and satellite communications for the military, security, and global telecommunications industries.

Bloggers and Journalists at DAC – Two Years Later

Bloggers and Journalist once squared off over their roles and access rights at DAC. Have the organizers of the biggest EDA trade show now found the right balance between these two groups?

FPGA’s Tackle Motor Control System

The need for more power efficient control of multiple motors has resulted in the inclusion of microcontroller and mixed signal devices into the fabric of FPGAs.

Hardware “Software” is not Software “Software”

As the EDA and semiconductor communities venture more fully into the realm of software development and applications, they must remember that software has a multitude of meanings.

EDA Focus Shifts To Software

A year ago it was all about developing hardware at the leading edge of Moore’s Law. Now the focus is on developing software.

Remote RF Telescope Bring Sci-Fi To Reality

The huge RF radio observatory at Arecibo, Puerto Rico has all of the key ingredients for a high-tech adventure movie. First, its location is remote, as it’s buried deep within the rainforest of a Caribbean island. Second, the sheer size of the radio telescope renders it sublime. It measures 305 m (1001 ft.) in diameter and more than 500 m from the jungle floor to the top of the moveable radio feed platform (see Figure 1). Unlike other astronomic R&D facilities in the United States, the observatory at Arecibo also is more than just a radio telescope. It also is a complete R&D facility. Its mission – in part – is to search for the stuff of science fiction stories ranging from extraterrestrials and gravity waves to asteroids that could devastate the Earth.

EDA Extends Board Design into Manufacturing

A recent EDA and PCB acquisition represents a significant merger between the worlds of electronic and mechanical manufacturing.

EDA Tool Vendor – A Rose by any other Name?

The "Bang" That Left The US Behind

Lower-Power Java Platforms

Movement from desktop to mobile changes the technical development and the business equation for the development language.

Is EDA Still EDA?

Is the Electronic Design Automation (EDA) tools market shrinking or growing? That depends greatly upon how you define EDA.

Freeman Dyson - Biotech vs Nanotech Continues

Social Media – Today’s Isle of the Lotus Eaters

Power7, Numonyx Acquisition and Apple-Adobe Battle

From new 64-core processors and memory acquisitions to software applications, the world of electronics continues to change. Here’s a few of this week’s tid-bits that caught my attention ...

Going Beyond and Returning to Reusability

Design for the Consumer Era is seen as the next iteration of the infamous Design-for-X paradigm shift by keynote presenter at DesignCon 2010.

Accessibility Trumps Accuracy In Today’s Hardware Models

Shrinking time-to-market windows and competition to keep end-product costs low have resulted in a growing usage of hardware prototypes and software algorithm models.

That's One Big Button - DesignCon10 Video

A Smaller Semiconductor Industry Moves Forward

What do Greenpeace, CES’10 and Low Power Technology have in Common?

My quest was simply to determine the low-power requirements necessary to receive good marks in Greenpeace’s "Guide to Greener Electronics." As with most such quests, mine led me through a thicket of related standards. But it wasn’t what I found that was surprising. What was missing turned out to be the real shocker!

Stranger than Fiction: Technology And Science Fiction

End User Report: Challenges In Wireless Audio Design

When most people think of wireless audio applications, they think of a Bluetooth headset that connects to their mobile phone. But a growing segment of the wireless audio market is occurring in the whole home connectivity space, where audio is CD rather than MP3 listening quality. How will this more stringent audio requirement play out in the whole home environment?

Stranger than Fiction: Technology And Science Fiction

Albert Einstein once said that imagination is more important than knowledge. So where do you go to find great imagination?

What Are They Designing?

A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs being designed by engineers using EDA tools were building full custom devices, and another 24% were building FPGAs. Only 9% were working on ASICs, although the ASICs tend to be large and extremely complex chips.

Chip Revenues Grow, but Software is the Future

Freeman Dyson Talks About Biotech vs Nanotech

ASIC Prototypers Target Specific Markets

Chip Vendors Find System Coverage Helps Bottom Line

Today’s newspapers and websites are cluttered with companies reporting increased revenues on lower sales. Simply put, this means that companies have laid off employees and cut other costs in order to show a profit. One big result of these cutbacks in workers, which this time included engineers and sometimes entire design teams, is that companies will have fewer resources to bring new products to market or to maintain existing product lines.

EDA Tech and Tool survey – Amazon and Dangdang certificates

Semiconductor Growth – When and Where?

Bloggers Turning into Journalist?!

Misinterpretation of Data – An Architectural Problem?

Engineers Should Pay Attention to M&As

Balancing Act Also Extends to Memory

A Career in Engineering: Is it worth it?

Impression of EDA and DAC'09

DAC Tuesday - From the Denali Party Floor

Lack of Pubs and Comm Skill of Engineers Spell Trouble

Press Credentials for Corporate Bloggers – Coverage at any cost?

Smaller, Faster and More Parasitic

Consumers love ever-smaller electronic products that have longer battery life and more features. For the chip developer, these “loves” translate to increased circuit performance and higher transistor density at lower and lower technology nodes, such as 45nm, 28nm and beyond. But these nodes are fraught with design and manufacturing challenges that weren’t really a problem at the relatively spacious geometries of 130nm and above.

Reader Wants Print, not Links

Why Sustainable and Green are Meaningless Terms to Designers

If you ask most engineers about green or sustainable electronics design, they’ll shrug their shoulders and say, “So what?” If you ask those same engineers about low power design, they’ll lean their shoulders forward and say, “Continue.” And if you ask their managers, the response will be, “You mean system-level design, don’t you?”

What do Engineers Want from Corporate vs Technology Press websites?

Low Power Design Reverses Outsourcing Trend

Exclusive Research: Looking Over The Chip Architect’s Shoulder To Spot Next Bull Market

Is there any truth to the news that the semiconductor market is in the beginning of a cyclical bull market?

Power and Placement - New Meanings in Green

Do Readers Care Who Pays the Editor?

Power Trump's Time-to-Market as Main Driver

Architectural Design Companies Drop ESL Moniker

More and more companies on the software or “soft” side of chip design are distancing themselves from the Electronic System Level (ESL) design terminology. Who can blame them? ESL has been so hyped that it’s come to mean the near-instantaneous generation of optimized RTL-based hardware from high-level software algorithms. Anyone involved in the rigorous exercise of performing architectural trade-off studies between chip power-performance-area constraints will tell you of the complexities involved with concept to hardware implementation of such designs.

What is the Connection Between Epitaxy and Optics?

Power - The One Variable Constant

Software Programmers Face Multicore Challenges

As multicore technology moves into the embedded systems, software developers face tool shortcomings, legacy code preservation and scalability challenges.

Economy Exacerbates Seasonal Decline in Chip Investigations

Synopsys Integrates Hardware Prototyping Tools

First Impressions: Cadence's Lip-Bu Tan

Adventures at DesignCon - Twitter Logs and a Gold Stocking Woman

Cadence Experiences Management Changes – Again

The Media is Dying? Catchy, But Inaccurate.

Cadence CTO Departs? Yes - It's True.

System-Level Design Community Gains Visibility as New Media

System-Level Design Community Makes MSNBC

Engineers And Social Media – The Untold Story

Are engineers really as inept and socially handicapped as many would believe? It’s popular to put down engineers as geeky and socially inept. In some cases, this stereotype is true. But would you be surprised to learn that yesterday’s engineers were the pioneers of social media—tools and usage—as we know it today?

Xilinx's Programmable Imperative

Engineers And Social Media – The Untold Story

Numbers Support Downturn - for now

Stereotypical Engineering Humor

Chip Starts - Are you an Optimist or Pessimist?

What do Technology and Social Media Clusters have in Common?

Chip Numbers Show Growth But Support Slowdown

Fate of Larger Technology Trade Publishers in Question

EDA User Rescue Plan

Happy Thanksgiving All!

Why Doesn't Our DAC Look Like This?

EDA Bloggers’ Birds-of-a-Feather

A Quick Look at Embedded Memory Trends

So, You Want to be a Chip Designer?

Cadence Eliminates at least 12% of Workforce

Mars Phoenix Twitter-style epitaph contest

Despite Dire News, Chip Design Starts may be on Rise

Nightmare on 802.11 Street - A Modern Halloween Tale!

Cadence - From Hunter to Haunted

Of Blog Vampires and Dead Kittens

LEGOs and the EDA Profession

Chips of the Wireless Swarm

Readers Gain with New Technology Community!

Welcome to System-Level Design

Green Power Moves Beyond the Buzz

High Tech US Acquisitions with Foreign Assets

Semiconductor R&D's Decline in the US

Solar Power Problems? - Just Call on a Stellar Engineer

Who needs publishers?

Financial Markets Yawn as Cadence-Mentor Ordeal Ends

What does Impinj, Virage and Intel have in common?

When is a blog not a blog?

Systems Beyond EDA's ESL

Beauty in Chip Failures

Another One (Pub) Bits the Dust

Virtutech's Software creates Hardware

Open Source Hardware and EDA tools

Watch Out, Cadence! The Hunter May Become the Hunted

Making Mentor Out As the Bad Guy?

My Videolog from DAC'08 - Grief from Jenna

Cadence-Mentor Battle Spurs Local Interest

EDA Community Alive with Opposition to Cadence Take-over of Mentor

Why Didn't Cadence Hold a Press Briefing on Acquisition?

Blogging Event Spurs Comments

From DAC - Three Pillars of IC Implementation

Informal Blogging Event at DAC Gains Interest

BoF for bloggers at DAC

The Truth is Out There...

What was the Antikythera Mechanism?

Note to Startups - Work on your Briefings

The Second Law of Technology

VC Investment Down, But Acquisitions Up?

Quick Impression of the Embedded Systems Conference '08

Wikipedia or Deletopedia

Weapons of mass construction

Time travel likely?

GlobalPress coverage

Check out our new website!

30% of Ninth Graders Will Drop Out

Standards vs IP vs Patents

Trends in EDA coverage

Killing Trees vs Manufacturing Toxins from Chip

EDN has a Potential Buyer?

Wikipedia, Digg - Use with caution

Beam me up, Scotty! Well, on second thought...

Publishing layoffs continue, thanks to the King's Consort

Would the last editor who leaves EDA please turn out the lights?

Most Under-rated Technologies

GooglePage - Google's Spin on a HomePage

EEG cap turns you into virtual Darth Vader

Darth Vader as Tomorrow's Blogger

Don’t go it alone - My Advice to new EDA/IC publications

Technological Obsolesce vs the Public Domain

Editor Works by Firelight to meet Deadlines

Free HAM class in Portland

Vendor as Publisher or A Retelling of the Wolf and the Dog

Trade editors as wolf

The Future is Back!

Why Books Will Survive

Portland Bridges are the Best!

Trends in EDA-Semi Trade Shows

The Dangerous Tome of Dr. Ray

A Family of Black Belts

American Innovation Driven by Immigrants

Zero-Degrees of Freedom at 45nm

At Large At IMEC: "To 3D or not 3D? When/How is the Question."

At Large: The IMEC ARRM2007 Press Review

Giants Sell-off Advanced TCA

DFM Feels Pull from EDA and Semi Worlds

EDA Media Industry at the CrossRoads

And then there were three...

Cadence Buyout Coincidence

Quick Impressions from DAC

Move over Multicore: Solid State Drives Are the Next Killer Technology

US Loses Technical Dominance, One Student at a Time

Silicon Forest’s High-Tech Community

Sage advisers or misguided padawans?

Happy Thanksgiving!

Transistor Cover-up at Bell Labs?

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