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Transistors Are A Growth Area Again

By James Hogan

I am increasingly becoming aware of semiconductor players that are turning to more custom physical design as they focus on high-volume, low-margin markets such as data storage and consumer devices.


These semiconductor players are finding it difficult to differentiate existing SoC designs from the competition, given very similar ASIC physical design and implementation approaches. Additionally, most of the leading edge SoC companies utilize foundries such as TSMC, so differentiating your design via process technology is also impossible.


This increased custom physical design content is taking four major forms: regular structures such as memory and datapath, analog blocks, custom digital and cell or macro development.


As it regards the rebirth of custom physical design ,there is an especially interesting trend at advanced technology nodes. Here the same logic process is being used for analog, memory and mixed signal designs all on one chip. These designs experience very difficult constraints. The memory and mixed signal portions have always needed a certain degree of custom design, but at advanced technologies this degree of custom is increasing. It is apparent that assisted-automation technology in the routing domain is critical to meet schedules in this new era of custom design.

Along with this routing automation it is becoming necessary to use “what if” analysis (embedded timing and extraction) to ensure that timing and power requirements can be met.


A number of semiconductor designers also are finding that when a digital SoC design closure involves multi-corner, multi-mode physical design optimization and power optimization, custom design can provide an alternative solution with higher productivity. In a custom design transistors and routing can be exactly sized to meet critical timing paths while also optimizing power. There is far less control and differentiation in a purely automated ASIC place-and-route paradigm and this can lead to a great number of ECO and place-and-route iterations.


As more of these high-volume, low-margin semiconductor devices often involve mixed signal and custom designed blocks, layout editors and custom physical design techniques are becoming more important for chip finishing and assembly of mixed signal devices. Key to using the layout editor as a “chip assembly” platform is design flow interoperability. The layout editing environment must embrace standards such as OpenAccess, PyCells and Tcl, and must include powerful automation technology for routing and analysis.



Slowly the EDA market players are beginning to come around to this rebirth of the custom design space. Cadence’s Virtuoso dominates this space today but emerging technology is coming from competitors. The SpringSoft Laker platform is doing well in Asia and they are adding key automation partnerships such as with Pyxis in the routing domain. Synopsys is behind but has stated that custom design is a growth area for the company and one in which it plans to invest heavily in 2009-2010. Magma has its Titan offering in this space and Mentor is working to add automation to its legacy offering, as well.



TSMC also has added some interest by joining the IPL Alliance. The IPL Alliance is an industry-wide collaborative effort to create and promote interoperable process design kit (PDK) standards. At the core of the IPL activity is Craiova’s PyCell efforts, which enables a new product that adds a higher level of automation for device-level placement of analog and custom elements called Helix. There is a general feeling that custom design is back in vogue and will provide one of the few growth areas for EDA in 2009.


Transistors are again the growth area for EDA. I never thought I would live long enough to say that again.

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