OCP-IP Publishes New “Intro to OCP” Book
Si2 Announces the OpenPDK v1.0 Standard “Open Process Specification comes to life”
Leaders Call Advanced Manufacturing Driver of U.S. Economy at GLOBALFOUNDRIES Symposium
Si2 Announces “OPS Comes to Life” Session for Si2 Roundup@DAC
OCP-IP Releases New Compliance Document into Member Review
OCP-IP Releases OCP 3.1 Specification into Member Review
Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference
OCP-IP Delivers Enhanced Transaction Generator Package
GSA Reports an Increase in April Semiconductor Funding Activity
Si2 Announces New Session for “Si2 Roundup@DAC”
GLOBALFOUNDRIES Fab 8 Adds Tools to Enable 3D Chip Stacking at 20nm and Beyond
Si2 Announces “Si2 Roundup@DAC: Standards in Action”
GSA Reports A Decrease in March Semiconductor Funding Activity
GLOBALFOUNDRIES Dresden Fab Ships 250,000th 32nm HKMG Wafer
IBM and GLOBALFOUNDRIES Begin First Production At New York's Latest Semiconductor Fab
- The world’s first truly global semiconductor foundry with expanding capacity
- The Guide to Success with High K Metal Gate (HKMG)
- GLOBALFOUNDRIES Unveils Industry's First 28nm Signoff-Ready Digital Design Flows
- GlobalShuttle is the MPW (Multi Project Wafer) program aimed at offering cost competitive vehicles for product prototyping, device characterization, IP validation, and design enablement.
- GTC 2011 - "Driving Innovation through True Collaboration" Capacity Crowds Attend in Santa Clara, Hsinchu, and Shanghai
Blogs
Collaborative Advantage
Si2 Roundup @ DAC: Standards in Action
If you are attending DAC this year, or still thinking about it, then read on -- you will not want to miss out on all the...
Pallab's Place
New Designs Focus on Devices
In the midst of big chip announcements (Intel’s IvyBridge at 22nm, Nvidia’s Kepler at 7B devices) the discussion has...
Real Talk from Real Intent
Poll
Affiliate Sponsors
Synopsys - Focus on Interoperability
Articles
Ain't No Mountain High Enough - Taking Interoperability to the System-Level
Developing a chip can be a daunting task. If you are the project lead, your boss is likely asking for aggressive and realistic schedules. You have to deal with demanding software ...
Site
Sponsors:
New White Papers
LTE-Advanced Signal Generation and Measurement Using SystemVue
Linking Early Mechatronic System Analysis to Physical Testing
Best Practice Development Processes for Medical Device FPGAs
Direct Power MOSFET Capacitance Measurement at 3000 V
Common Pitfalls in PCI Express Design
Increasing Revenue Through Continuously Optimized Data Center Management
Featured Videos/Podcasts
EECatalog Tech Videos
Chip Design on Twitter
Spotlight On RF and Microwave
Spotlight On
Agilent EEsof EDA
- Watch 30-Second Productivity Demos—Win $100
- How to make EDA designs more robust Webcast
- View the Innovations in EDA Webcast Archives
- Watch the Video UWB Radar Signal Generation
- Watch the Genesys Swept Analysis Video
- Download "Securing Successful First-Pass Component Design" App Note
- Power Model Complexity Grows
- Material Effects: Trading Performance For Power
- Low Power Dominates CES
- Editor's Note: Technology Crossover Ahead
- Absolute Power: 4G LTE vs. 3G
Sponsored by:
- The Next SoCs
- Derivative Designs Demand Discipline
- Software Takes Control
- Editor's Note: The Next Frontiers
- ESL Edge: Getting Ahead Of Yourself
Sponsored by:
Newsletters
Resource Catalogs and Guides
- Chip Design Resource Catalog
- Chip Design Buyers' Guide
- Interoperability Guides
- IP Solutions Resource Catalog
- Valuable Resources
 |
||||
 |
||||
|
||||
|
||||
|
HOME | ABOUT | SUBSCRIBE | ADVERTISE | CONTACT US | PRIVACY STATEMENT All materials on this site Copyright © 2012 Extension Media LLC. All rights reserved. |