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New White Papers
Evolving the Coverage-driven Verification Flow
Power Consumption at 40 and 45 nm
Accurately Analyzing Power in a Simulink Software Model-Based Design Flow
Capabilities to Maximize Productivity for FPGA Debug and Verification
Synopsys White Paper: Understanding the real cost of prototyping hardware
The PSP Model in RF CMOS Design
Blogs
JB's Circuit
Going Beyond and Returning to Reusability
Design for the Consumer Era is seen as the next iteration of the infamous Design-for-X paradigm shift by keynote presenter at...
Tuning into Jim
Going, Going, Almost Gone
There has been a trend over the past several years in the electronics community. It has been driven by the dismal economy...
EDA Thoughts
Carbon Footprint is Good For ICs
IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs. | Photo...
Wizards of Microwave
Using EM to Design DGS Structures
A Defective Ground Structure (DGS) is an intentionally designed defect on a ground plan, which creates additional effective...
Poll
•Synopsys Interoperability Guide
SYNOPSYS INTEROPERABILITY GUIDE
Articles
Strengthening the Design Ecosystem Through Interoperability
The term "interoperability" is a lightening rod for both for customers and vendors in the EDA industry. While the concept is clear, enabling that interoperability proves to be more ...
Alliance and Interoperability Programs Enable Future Tool Flows
Collaboration and partnerships continue to be major activities in the EDA and semiconductor worlds. One was to foster collaboration is through a mechanism like Synopsys's Partner p ...
- Experts At The Table: The Reliability Factor
- Verifying Low-Power Designs
- Low-Power Architectures Go Mainstream
- Editor’s Note: The Prius Wake Up Call
- Absolute Power: Fun Facts for the New Year
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Featured Videos/Podcasts
IP Search
Resource Catalogs and Guides
- Chip Design Resource Catalog
- Chip Design Buyers' Guide
- Interoperability Guides
- IP Solutions Resource Catalog
- Valuable Resources
- Visit Dot.Org
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