{
  "top": "tb",
  "tools": {
    "iverilog": "Icarus Verilog version 13.0 (stable) (v13_0)",
    "python": "3.12.14"
  },
  "commands": [
    "iverilog -g2012 -s tb -o simulation counter.sv tb.sv",
    "vvp simulation"
  ],
  "inputs": [
    {
      "path": "counter.sv",
      "role": "rtl"
    },
    {
      "path": "tb.sv",
      "role": "testbench"
    },
    {
      "path": "clock.sdc",
      "role": "constraints"
    }
  ],
  "limits": [
    "clock.sdc is recorded but not consumed by this RTL simulation",
    "No synthesis, timing closure, power intent or physical verification was performed"
  ]
}