// SPDX-License-Identifier: MIT
`timescale 1ns/1ps
module tb;
  reg clk = 0;
  reg reset_n = 0;
  reg pulse = 0;
  wire [3:0] count;
  pulse_count dut(clk, reset_n, pulse, count);
  always #5 clk = ~clk;
  initial begin
    @(negedge clk); reset_n = 1; pulse = 1;
    repeat (3) @(negedge clk);
    pulse = 0;
    if (count !== 3) $fatal(1, "count mismatch");
    $display("PASS count=%0d", count);
    $finish;
  end
endmodule