# RTL and Yosys generic (proc/opt) netlist comparison

Original code and generated original generic (proc/opt) netlist: MIT. Exact tool sources:

- Icarus Verilog 13.0: dfeee909ed9f20b4870dd93423156c0170c0e1ff.
- Verilator 5.052: ea338be98e1e838d3518809ce8899f85a009963c.
- Yosys 0.70+post: the binary reports revision `0c11ea098be065e585a90a06e7b7da49936cf231`. The official `v0.70` tag is `28ba3cb926fe376fa05ebfc1b921747d011d4557`, not that binary-reported revision.

The article prints design.sv and tb.sv verbatim. Run with those files in the working directory and installed tools on PATH:

```sh
yosys -T -s synthesize.ys
yosys -T -s equivalence.ys
iverilog -g2012 -gstrict-expr-width -s tb -o rtl.vvp design.sv tb.sv
vvp rtl.vvp
iverilog -g2012 -gstrict-expr-width -s tb -o gate.vvp netlist.v tb.sv
vvp gate.vvp
verilator --binary --quiet-build --quiet-stats --quiet-exit --timing --language 1800-2012 --x-assign 0 --x-initial 0 -Wno-fatal --top-module tb --Mdir obj_rtl design.sv tb.sv
./obj_rtl/Vtb +verilator+quiet
verilator --binary --quiet-build --quiet-stats --quiet-exit --timing --language 1800-2012 --x-assign 0 --x-initial 0 -Wno-fatal --top-module tb --Mdir obj_netlist netlist.v tb.sv
./obj_netlist/Vtb +verilator+quiet
```

The delivered Yosys generic (proc/opt) netlist has an MIT comment prepended to Yosys output before it was simulated. It contains no library model. Rebuilding it may change this comment or tool header; record the generated bytes used for your new run. Both RTL and the generic (proc/opt) netlist execute the same testbench. Build in a path without spaces for this Verilator build configuration. Do not publish executables or obj directories.

The initial reserved-keyword naming attempt remains under rejected-naming-attempt/ with separate rejection logs. It is not the source used for the passing simulation. Source compilation errors were not suppressed to make the current source pass. The final testbench also adds `a = 1; #1; a = 0; #1;` before the b-only change, establishing the previous sensitivity-list value. This stimulus change accompanies the identifier rename.

Public logs under ../../measurements/printed-hdl/P07-*.json contain actual commands, version pins, source hashes, return codes and outputs. Absolute tool/build paths use symbolic placeholders; automatic runtime CPU/memory summaries are omitted. Unknown outputs are observations, with no cross-tool x-equivalence claim. The equivalence check covers only the signed-extension modules, not the complete intentionally faulty design. No timing or power result is established.

The Verilator executable hash `098b09b1…` identifies the `bin/verilator` Perl driver; `097580dd…` identifies its `bin/verilator_bin` native compiler from the same 5.052 installation. Current records name and hash both files. Earlier P8 records are preserved under `../../measurements/printed-hdl/earlier-p8/`.