// SPDX-License-Identifier: MIT
/* Generated by Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334) */

module comparison_pair(clk, reset, a, b, select_bit, enable, data_bit, narrow, sensitivity_bad, sensitivity_fixed, width_bad, width_fixed, if_bad, case_bad, case_fixed, if_fixed, race_a_bad, race_b_bad, race_a_fixed, race_b_fixed, initial_only
, reset_fixed);
  input clk;
  wire clk;
  input reset;
  wire reset;
  input a;
  wire a;
  input b;
  wire b;
  input select_bit;
  wire select_bit;
  input enable;
  wire enable;
  input data_bit;
  wire data_bit;
  input [7:0] narrow;
  wire [7:0] narrow;
  output sensitivity_bad;
  wire sensitivity_bad;
  output sensitivity_fixed;
  wire sensitivity_fixed;
  output [15:0] width_bad;
  wire [15:0] width_bad;
  output [15:0] width_fixed;
  wire [15:0] width_fixed;
  output if_bad;
  wire if_bad;
  output case_bad;
  wire case_bad;
  output case_fixed;
  wire case_fixed;
  output if_fixed;
  wire if_fixed;
  output race_a_bad;
  reg race_a_bad;
  output race_b_bad;
  reg race_b_bad;
  output race_a_fixed;
  reg race_a_fixed;
  output race_b_fixed;
  reg race_b_fixed;
  output initial_only;
  reg initial_only = 1'h1;
  output reset_fixed;
  reg reset_fixed;
  wire _00_;
  always @(posedge clk)
    if (reset) race_b_bad <= 1'h1;
    else race_b_bad <= race_a_bad;
  always @(posedge clk)
    if (reset) race_a_fixed <= 1'h0;
    else race_a_fixed <= race_b_fixed;
  always @(posedge clk)
    if (reset) race_b_fixed <= 1'h1;
    else race_b_fixed <= race_a_fixed;
  always @(posedge clk)
    if (reset) race_a_bad <= 1'h0;
    else race_a_bad <= race_b_bad;
  always @(posedge clk)
    if (reset) reset_fixed <= 1'h0;
    else if (enable) reset_fixed <= data_bit;
  always @(posedge clk)
    if (enable) initial_only <= data_bit;
  function [0:0] _07_;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    casez (s) // synopsys parallel_case
      2'b?1:
        _07_ = b[0:0];
      2'b1?:
        _07_ = b[1:1];
      default:
        _07_ = a;
    endcase
  endfunction
  assign case_bad = _07_(1'hx, { b, a }, { _00_, select_bit });
  assign _00_ = ~ select_bit;
  assign if_bad = select_bit ? a : b;
  assign sensitivity_bad = a ^ b;
  assign if_fixed = if_bad;
  assign case_fixed = case_bad;
  assign width_fixed = { narrow[7], narrow[7], narrow[7], narrow[7], narrow[7], narrow[7], narrow[7], narrow[7], narrow };
  assign width_bad = { 8'h00, narrow };
  assign sensitivity_fixed = sensitivity_bad;
endmodule