# Timing constraints: reproduction

The original `timing_demo.v`, `check.tcl` and `prepare_library.py` are MIT licensed. The cell library and its converter retain their upstream licences and are not included. Only source URLs, hashes and the original preparation script are distributed here. Keep all fetched library files and tool builds outside the published package.

## Pins

- OpenSTA 3.1.0, official source `https://github.com/parallaxsw/OpenSTA.git`, commit `b3e1b3989809e1c70f265a9e7be33438c3ebf8bf`.
- SkyWater HD library, Apache-2.0, commit `ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1`.
- Official JSON-to-Liberty converter, `https://github.com/google/skywater-pdk.git`, commit `7198cf647113f56041e02abf3eb623692820c5e1`.
- Converter dependency `dataclasses-json==0.6.7`; preparation verified with Python 3.9.6. The preparation script verifies every fetched byte against `library-provenance.json` and verifies the final Liberty hash.
- Executed timing environment: macOS 27.0.1, arm64, Tcl 8.6.18. Tool builds are external prerequisites.

## Prepare the external timing library

From this example directory, with Python and Git available:

```sh
TIMING_EXTERNAL="$(mktemp -d)"
python3 -m venv "$TIMING_EXTERNAL/python"
"$TIMING_EXTERNAL/python/bin/pip" install 'dataclasses-json==0.6.7'
git clone https://github.com/google/skywater-pdk.git "$TIMING_EXTERNAL/skywater-pdk"
git -C "$TIMING_EXTERNAL/skywater-pdk" checkout 7198cf647113f56041e02abf3eb623692820c5e1
PYTHONPATH="$TIMING_EXTERNAL/skywater-pdk/scripts/python-skywater-pdk" \
  "$TIMING_EXTERNAL/python/bin/python" prepare_library.py "$TIMING_EXTERNAL/cells"
export CELL_LIB="$TIMING_EXTERNAL/cells/subset.lib"
```

Expected final preparation message: `Verified library inputs and generated subset.lib`. The output hash is `fb7c3b98b4ef971186f79bc4ac1f7181f7655de5b96bbce54666c0b97e1bc5b9`. The three cells are `sky130_fd_sc_hd__buf_1`, `sky130_fd_sc_hd__inv_1` and `sky130_fd_sc_hd__dfxtp_1`; the timing corner is typical 25 °C, 1.8 V. No cell equations or timing tables are copied into the package.

## Execute the six cases

Use `sta` built from the commit above. For an isolated Tcl installation, set `TCL_LIBRARY` to that installation's Tcl script directory before invoking `sta`. That is an installation setting, not an additional timing constraint.

```sh
CASE=baseline sta -no_init -exit check.tcl
CASE=multicycle_setup sta -no_init -exit check.tcl
CASE=multicycle_pair sta -no_init -exit check.tcl
CASE=false_path sta -no_init -exit check.tcl
CASE=asynchronous sta -no_init -exit check.tcl
CASE=coverage_audit sta -no_init -exit check.tcl
```

Each command starts from a new timing design. `baseline` uses a 0.90 ns primary clock and an independent 1.30 ns clock. `coverage_audit` changes only the primary period to 1.10 ns and applies the asynchronous grouping. All cases use ideal clocks, zero wire parasitics, 0.05 ns clock transition, 0.05 ns setup uncertainty, 0.45 ns hold uncertainty and 0.01 pF output loads.

## Expected observations

| Case | Observation under the printed conditions |
| --- | --- |
| Baseline | Slow setup −0.063422 ns, hold +0.406981 ns; fast setup +0.372329 ns, hold −0.033411 ns. |
| Setup-only multicycle | Slow setup +0.836578 ns and hold −0.493019 ns. |
| Paired multicycle | Slow setup +0.836578 ns and hold +0.406981 ns. |
| False path | No selected slow-capture path remains in the report. |
| Asynchronous groups | Independent capture disappears; generated capture remains related and reported. |
| Coverage audit | Maximum-delay worst slack +0.136578 ns; unconstrained output warning remains. |

The complete reports, UTC timestamps and executed input hashes are in `../../measurements/printed-hdl/P06-opensta.json`. Warnings about `unconstrained_out` are deliberate. The process exit code does not establish positive slack or complete constraints.

The netlist includes an intentionally direct asynchronous crossing and lacks functional permission for the multicycle exception. It is a timing-analysis demonstration, not a safe crossing implementation or a sign-off design. No synthesis, placement, routing, parasitic extraction, clock-startup simulation or silicon validation was run.