// SPDX-License-Identifier: MIT
`timescale 1ns/1ps
module bounded_adder #(parameter FIX = 0)(
  input logic enable,
  input logic [1:0] a, b,
  output logic [1:0] result
);
  logic [2:0] wide;
  generate
    if (FIX) begin : corrected
      always_comb begin
        wide = {1'b0, a} + {1'b0, b};
        if (!enable) result = 0;
        else if (wide > 3) result = 3;
        else result = wide[1:0];
      end
    end else begin : broken
      always_comb begin
        wide = {1'b0, a} + {1'b0, b};
        if (enable) result = wide[1:0];
        else result = 0;
      end
    end
  endgenerate
endmodule
/* verilator coverage_off */
module tb #(parameter FIX = 0);
  logic enable = 0;
  logic [1:0] a = 0, b = 0, result;
  integer extended = 0;
  integer disabled_seen = 0, ordinary_seen = 0, overflow_seen = 0;
  integer mismatches = 0;
  bounded_adder #(.FIX(FIX)) dut(enable, a, b, result);
  task sample(input logic en, input logic [1:0] aa, bb);
    integer expected, total;
    enable = en;
    a = aa;
    b = bb;
    #1;
    total = int'(aa) + int'(bb);
    expected = !en ? 0 : total > 3 ? 3 : total;
    if (!en) disabled_seen = disabled_seen + 1;
    else if (total > 3) overflow_seen = overflow_seen + 1;
    else ordinary_seen = ordinary_seen + 1;
    if (result !== 2'(expected)) mismatches = mismatches + 1;
    $display("enable=%0d a=%0d b=%0d expected=%0d result=%0d",
             en, aa, bb, expected, result);
  endtask
  initial begin
    if ($value$plusargs("extended=%d", extended)) begin end
    sample(0, 1, 1);
    sample(1, 1, 1);
    if (extended) sample(1, 3, 1);
    $display("FUNCTIONAL disabled=%0d ordinary=%0d overflow=%0d",
             disabled_seen, ordinary_seen, overflow_seen);
    $display("CHECKER mismatches=%0d", mismatches);
    $finish;
  end
endmodule